1.1 --- a/modules/bluespec/Pygar/core/#Processor.bsv#	Tue May 04 12:14:24 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/#Processor.bsv#	Tue May 04 18:54:54 2010 -0400
     1.3 @@ -30,8 +30,10 @@
     1.4  import FIFOF::*;
     1.5  import SFIFO::*;
     1.6  import RWire::*;
     1.7 +
     1.8  import Trace::*;
     1.9  import BFIFO::*;
    1.10 +import MemTypes::*;
    1.11  import ProcTypes::*;
    1.12  import BRegFile::*;
    1.13  import BranchPred::*;
    1.14 @@ -44,7 +46,7 @@
    1.15  
    1.16  // Local includes
    1.17  //`include "asim/provides/processor_library.bsh" (included above directly)
    1.18 -`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
    1.19 +
    1.20  `include "asim/provides/common_services.bsh"
    1.21  `include "asim/dict/STATS_PROCESSOR.bsh"
    1.22  `include "asim/provides/processor_library.bsh"
    1.23 @@ -75,6 +77,7 @@
    1.24  
    1.25    // Interface to Audio Pipeline
    1.26    interface Get#(AudioProcessorUnit) sampleOutput;
    1.27 +  interface Put#(AudioProcessorUnit) sampleInput;
    1.28  	
    1.29  endinterface
    1.30  
    1.31 @@ -225,12 +228,6 @@
    1.32  module  [CONNECTED_MODULE] mkProc( Proc );
    1.33  
    1.34     //-----------------------------------------------------------
    1.35 -   // Debug port
    1.36 -   
    1.37 -   ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();   
    1.38 -
    1.39 -   
    1.40 -   //-----------------------------------------------------------
    1.41     // State
    1.42  
    1.43     // Standard processor state
    1.44 @@ -248,10 +245,13 @@
    1.45     FIFO#(PCStat)           pcQ <-mkSizedFIFO(3);
    1.46     SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
    1.47  
    1.48 +   // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
    1.49     Reg#(Bit#(32)) cp0_tohost   <- mkReg(0);
    1.50     Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
    1.51     Reg#(Bool)     cp0_statsEn  <- mkReg(False);
    1.52 -
    1.53 +   Reg#(Bool)     cp0_audioEOF <- mkReg(False);  // Register to let code that EOF is reached
    1.54 +   Reg#(Bool)     cp0_progComp <- mkReg(False);  // Register to let processor know that the program is complete (as this terminates)
    1.55 +    
    1.56     // Memory request/response state
    1.57     
    1.58     FIFO#(InstReq)  instReqQ    <- mkBFIFO1();
    1.59 @@ -266,8 +266,8 @@
    1.60  
    1.61  
    1.62     // Statistics state (2010)
    1.63 -//   Reg#(Stat) num_cycles <- mkReg(0);
    1.64 -//   Reg#(Stat) num_inst <- mkReg(0);
    1.65 +   //   Reg#(Stat) num_cycles <- mkReg(0);
    1.66 +   //   Reg#(Stat) num_inst <- mkReg(0);
    1.67  
    1.68     //Or:
    1.69     // Statistics state
    1.70 @@ -486,11 +486,14 @@
    1.71  
    1.72        // -- Cop0 ------------------------------------------------------
    1.73        
    1.74 -      tagged MTC0  .it : 
    1.75 +      tagged MTC0  .it : //Recieve things from host computer
    1.76  	 begin
    1.77 +	    $display( " PROCESSOR MTC0 call\n");
    1.78              case ( it.cop0dst )
    1.79  	       5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
    1.80  	       5'd21 : cp0_tohost  <= truncate(rf.rd1(it.rsrc));
    1.81 +	       5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
    1.82 + 	       5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc))));  //Bit size is 16 not 32 
    1.83  	       default :
    1.84  	       $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
    1.85  	    endcase
    1.86 @@ -498,13 +501,27 @@
    1.87  	 end
    1.88  
    1.89  //this is host stuff?
    1.90 -      tagged MFC0  .it :
    1.91 +      tagged MFC0  .it :  //Things out
    1.92  	 begin
    1.93 +	    $display( " PROCESSOR MFC0 call\n");
    1.94              case ( it.cop0src )
    1.95  	    // not actually an ALU instruction but don't have the format otherwise
    1.96                 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
    1.97                 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
    1.98                 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost   });
    1.99 +	       5'd25 : begin
   1.100 +			  $display( "**** EOF Requested\n ");
   1.101 +			  wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) });  // Reading clears bit
   1.102 +			  cp0_audioEOF <= False;
   1.103 +		       end
   1.104 +	       5'd28 : begin
   1.105 +			  $display( "***** Reqesting Sample \n");
   1.106 +			  let sample = inAudioFifo.first();        // is this going to cause perf. delay?
   1.107 +			  if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF  
   1.108 +	      		     wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) });  // do I need pack?
   1.109 +			  else $display ( "Audio File EOF Reached.  Invalid sample request.");
   1.110 +			  inAudioFifo.deq();
   1.111 +		       end
   1.112                default : 
   1.113                  $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
   1.114              endcase
   1.115 @@ -559,41 +576,27 @@
   1.116        num_cycles.incr();
   1.117    endrule
   1.118  
   1.119 -(* conservative_implicit_conditions *)
   1.120 -  rule handleCPUToHost;
   1.121 -   let req <- server_stub.acceptRequest_ReadCPUToHost();
   1.122 -    case (req)
   1.123 -     0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
   1.124 -     1: server_stub.sendResponse_ReadCPUToHost(pc);
   1.125 -     2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
   1.126 -    endcase
   1.127 +
   1.128 + // for now, we don't do anything.
   1.129 +//  rule connectAudioReqResp;
   1.130 +//    $display("rlm: PROCESSOR copies a datum\n");
   1.131 +//    outAudioFifo.enq(inAudioFifo.first());
   1.132 +//    inAudioFifo.deq;
   1.133 +//  endrule
   1.134 +
   1.135 +  rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
   1.136 +     $display (" Proc Says End Audio Flag Set ");
   1.137 +     cp0_audioEOF <= True;
   1.138 +     inAudioFifo.deq;
   1.139    endrule
   1.140  
   1.141 - // for now, we don't do anything.
   1.142 -  rule connectAudioReqResp;
   1.143 -//    $display("rlm: PROCESSOR copies a datum\n");
   1.144 -    outAudioFifo.enq(inAudioFifo.first());
   1.145 -    inAudioFifo.deq;
   1.146 +  rule sendAudioEnd (cp0_progComp);
   1.147 +     $display (" PROCESSOR Says Program Complete ");
   1.148 +     outAudioFifo.enq(tagged EndOfFile);
   1.149 +     cp0_progComp <= False;  //only send one.  And functions to reset
   1.150    endrule
   1.151  
   1.152 -  // Server items & rules:
   1.153     
   1.154 -   rule feedInput;
   1.155 -     let command <- server_stub.acceptRequest_SendUnprocessedStream();
   1.156 -     AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
   1.157 -     if(ctrl == EndOfFile)
   1.158 -	begin
   1.159 -//	  $display("lsp: PROCESSOR received EOF   ");
   1.160 -          inAudioFifo.enq(tagged EndOfFile);
   1.161 -       end
   1.162 -     else 
   1.163 -	begin
   1.164 -//	  $display("lsp: PROCESSOR received Data   ");
   1.165 -          inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
   1.166 -       end
   1.167 -   endrule     
   1.168 -  
   1.169 - 
   1.170    //-----------------------------------------------------------
   1.171    // Methods
   1.172  
   1.173 @@ -609,17 +612,20 @@
   1.174  
   1.175    interface Get statsEn_get = toGet(asReg(cp0_statsEn));
   1.176  
   1.177 -//  interface CPUToHost tohost;
   1.178 -//    method Bit#(32) cpuToHost(int req);
   1.179 -//      return (case (req)
   1.180 -//       0: cp0_tohost;
   1.181 -//       1: pc;
   1.182 -//       2: zeroExtend(pack(stage));
   1.183 -//      endcase);
   1.184 -//    endmethod
   1.185 -//  endinterface
   1.186 -     
   1.187 +  /*
   1.188 +  interface CPUToHost tohost;
   1.189 +    method Bit#(32) cpuToHost(int req);
   1.190 +      return (case (req)
   1.191 +       0: cp0_tohost;
   1.192 +       1: pc;
   1.193 +       2: zeroExtend(pack(stage));
   1.194 +      endcase);
   1.195 +    endmethod
   1.196 +  endinterface
   1.197 +  */
   1.198 +   
   1.199    interface Get sampleOutput = fifoToGet(outAudioFifo);
   1.200 +  interface Put sampleInput = fifoToPut(inAudioFifo);
   1.201  
   1.202  endmodule
   1.203