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comparison modules/bluespec/Pygar/core/#Processor.bsv# @ 36:99519a031813 pygar svn.37

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[svn r37] moved the server into audioCorePipeline
author punk
date Tue, 04 May 2010 18:54:54 -0400
parents f5dfbe28fa59
children 2b18894f75e2
comparison
equal deleted inserted replaced
35:14f7a7ace3f5 36:99519a031813
28 28
29 import FIFO::*; 29 import FIFO::*;
30 import FIFOF::*; 30 import FIFOF::*;
31 import SFIFO::*; 31 import SFIFO::*;
32 import RWire::*; 32 import RWire::*;
33
33 import Trace::*; 34 import Trace::*;
34 import BFIFO::*; 35 import BFIFO::*;
36 import MemTypes::*;
35 import ProcTypes::*; 37 import ProcTypes::*;
36 import BRegFile::*; 38 import BRegFile::*;
37 import BranchPred::*; 39 import BranchPred::*;
38 //import PathTypes::*; This is only there to force the debugging 40 //import PathTypes::*; This is only there to force the debugging
39 41
42 `include "asim/provides/soft_connections.bsh" 44 `include "asim/provides/soft_connections.bsh"
43 `include "asim/provides/common_services.bsh" 45 `include "asim/provides/common_services.bsh"
44 46
45 // Local includes 47 // Local includes
46 //`include "asim/provides/processor_library.bsh" (included above directly) 48 //`include "asim/provides/processor_library.bsh" (included above directly)
47 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" 49
48 `include "asim/provides/common_services.bsh" 50 `include "asim/provides/common_services.bsh"
49 `include "asim/dict/STATS_PROCESSOR.bsh" 51 `include "asim/dict/STATS_PROCESSOR.bsh"
50 `include "asim/provides/processor_library.bsh" 52 `include "asim/provides/processor_library.bsh"
51 53
52 // Local includes. Look for the correspondingly named .awb files 54 // Local includes. Look for the correspondingly named .awb files
73 // // Interface to host 75 // // Interface to host
74 // interface CPUToHost tohost; 76 // interface CPUToHost tohost;
75 77
76 // Interface to Audio Pipeline 78 // Interface to Audio Pipeline
77 interface Get#(AudioProcessorUnit) sampleOutput; 79 interface Get#(AudioProcessorUnit) sampleOutput;
80 interface Put#(AudioProcessorUnit) sampleInput;
78 81
79 endinterface 82 endinterface
80 83
81 //The full interface for this is as below in the common file for audioProcessorTypes.bsv 84 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
82 //interface AudioOut; 85 //interface AudioOut;
223 //(* synthesize *) 226 //(* synthesize *)
224 227
225 module [CONNECTED_MODULE] mkProc( Proc ); 228 module [CONNECTED_MODULE] mkProc( Proc );
226 229
227 //----------------------------------------------------------- 230 //-----------------------------------------------------------
228 // Debug port
229
230 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
231
232
233 //-----------------------------------------------------------
234 // State 231 // State
235 232
236 // Standard processor state 233 // Standard processor state
237 234
238 Reg#(Addr) pc <- mkReg(32'h00001000); 235 Reg#(Addr) pc <- mkReg(32'h00001000);
246 243
247 // Pipelines 244 // Pipelines
248 FIFO#(PCStat) pcQ <-mkSizedFIFO(3); 245 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
249 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); 246 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
250 247
248 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
251 Reg#(Bit#(32)) cp0_tohost <- mkReg(0); 249 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
252 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); 250 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
253 Reg#(Bool) cp0_statsEn <- mkReg(False); 251 Reg#(Bool) cp0_statsEn <- mkReg(False);
254 252 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
253 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
254
255 // Memory request/response state 255 // Memory request/response state
256 256
257 FIFO#(InstReq) instReqQ <- mkBFIFO1(); 257 FIFO#(InstReq) instReqQ <- mkBFIFO1();
258 FIFO#(InstResp) instRespQ <- mkFIFO(); 258 FIFO#(InstResp) instRespQ <- mkFIFO();
259 259
264 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO; 264 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
265 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO; 265 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
266 266
267 267
268 // Statistics state (2010) 268 // Statistics state (2010)
269 // Reg#(Stat) num_cycles <- mkReg(0); 269 // Reg#(Stat) num_cycles <- mkReg(0);
270 // Reg#(Stat) num_inst <- mkReg(0); 270 // Reg#(Stat) num_inst <- mkReg(0);
271 271
272 //Or: 272 //Or:
273 // Statistics state 273 // Statistics state
274 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT); 274 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
275 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT); 275 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
484 branchTaken = True; 484 branchTaken = True;
485 end 485 end
486 486
487 // -- Cop0 ------------------------------------------------------ 487 // -- Cop0 ------------------------------------------------------
488 488
489 tagged MTC0 .it : 489 tagged MTC0 .it : //Recieve things from host computer
490 begin 490 begin
491 $display( " PROCESSOR MTC0 call\n");
491 case ( it.cop0dst ) 492 case ( it.cop0dst )
492 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); 493 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
493 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); 494 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
495 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
496 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32
494 default : 497 default :
495 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); 498 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
496 endcase 499 endcase
497 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be. 500 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
498 end 501 end
499 502
500 //this is host stuff? 503 //this is host stuff?
501 tagged MFC0 .it : 504 tagged MFC0 .it : //Things out
502 begin 505 begin
506 $display( " PROCESSOR MFC0 call\n");
503 case ( it.cop0src ) 507 case ( it.cop0src )
504 // not actually an ALU instruction but don't have the format otherwise 508 // not actually an ALU instruction but don't have the format otherwise
505 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); 509 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
506 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); 510 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
507 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); 511 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
512 5'd25 : begin
513 $display( "**** EOF Requested\n ");
514 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit
515 cp0_audioEOF <= False;
516 end
517 5'd28 : begin
518 $display( "***** Reqesting Sample \n");
519 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
520 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
521 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
522 else $display ( "Audio File EOF Reached. Invalid sample request.");
523 inAudioFifo.deq();
524 end
508 default : 525 default :
509 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); 526 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
510 endcase 527 endcase
511 end 528 end
512 529
557 rule inc_num_cycles; 574 rule inc_num_cycles;
558 if ( cp0_statsEn ) 575 if ( cp0_statsEn )
559 num_cycles.incr(); 576 num_cycles.incr();
560 endrule 577 endrule
561 578
562 (* conservative_implicit_conditions *) 579
563 rule handleCPUToHost; 580 // for now, we don't do anything.
564 let req <- server_stub.acceptRequest_ReadCPUToHost(); 581 // rule connectAudioReqResp;
565 case (req) 582 // $display("rlm: PROCESSOR copies a datum\n");
566 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); 583 // outAudioFifo.enq(inAudioFifo.first());
567 1: server_stub.sendResponse_ReadCPUToHost(pc); 584 // inAudioFifo.deq;
568 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage))); 585 // endrule
569 endcase 586
587 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
588 $display (" Proc Says End Audio Flag Set ");
589 cp0_audioEOF <= True;
590 inAudioFifo.deq;
570 endrule 591 endrule
571 592
572 // for now, we don't do anything. 593 rule sendAudioEnd (cp0_progComp);
573 rule connectAudioReqResp; 594 $display (" PROCESSOR Says Program Complete ");
574 // $display("rlm: PROCESSOR copies a datum\n"); 595 outAudioFifo.enq(tagged EndOfFile);
575 outAudioFifo.enq(inAudioFifo.first()); 596 cp0_progComp <= False; //only send one. And functions to reset
576 inAudioFifo.deq;
577 endrule 597 endrule
578 598
579 // Server items & rules: 599
580
581 rule feedInput;
582 let command <- server_stub.acceptRequest_SendUnprocessedStream();
583 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
584 if(ctrl == EndOfFile)
585 begin
586 // $display("lsp: PROCESSOR received EOF ");
587 inAudioFifo.enq(tagged EndOfFile);
588 end
589 else
590 begin
591 // $display("lsp: PROCESSOR received Data ");
592 inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
593 end
594 endrule
595
596
597 //----------------------------------------------------------- 600 //-----------------------------------------------------------
598 // Methods 601 // Methods
599 602
600 interface Client imem_client; 603 interface Client imem_client;
601 interface Get request = fifoToGet(instReqQ); 604 interface Get request = fifoToGet(instReqQ);
607 interface Put response = fifoToPut(dataRespQ); 610 interface Put response = fifoToPut(dataRespQ);
608 endinterface 611 endinterface
609 612
610 interface Get statsEn_get = toGet(asReg(cp0_statsEn)); 613 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
611 614
612 // interface CPUToHost tohost; 615 /*
613 // method Bit#(32) cpuToHost(int req); 616 interface CPUToHost tohost;
614 // return (case (req) 617 method Bit#(32) cpuToHost(int req);
615 // 0: cp0_tohost; 618 return (case (req)
616 // 1: pc; 619 0: cp0_tohost;
617 // 2: zeroExtend(pack(stage)); 620 1: pc;
618 // endcase); 621 2: zeroExtend(pack(stage));
619 // endmethod 622 endcase);
620 // endinterface 623 endmethod
621 624 endinterface
625 */
626
622 interface Get sampleOutput = fifoToGet(outAudioFifo); 627 interface Get sampleOutput = fifoToGet(outAudioFifo);
628 interface Put sampleInput = fifoToPut(inAudioFifo);
623 629
624 endmodule 630 endmodule
625 631