1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/core/sim/bdir_dut/Bridge.bi	Tue Apr 13 17:34:33 2010 -0400
     1.3 @@ -0,0 +1,137 @@
     1.4 +signature Bridge where {
     1.5 +import ¶Assert®¶;
     1.6 +		
     1.7 +import ¶ConfigReg®¶;
     1.8 +		   
     1.9 +import ¶Counter®¶;
    1.10 +		 
    1.11 +import ¶DReg®¶;
    1.12 +	      
    1.13 +import ¶EdgeDetect®¶;
    1.14 +		    
    1.15 +import ¶FIFOF_®¶;
    1.16 +		
    1.17 +import ¶FIFOF®¶;
    1.18 +	       
    1.19 +import ¶FIFO®¶;
    1.20 +	      
    1.21 +import ¶HList®¶;
    1.22 +	       
    1.23 +import ¶Inout®¶;
    1.24 +	       
    1.25 +import ¶List®¶;
    1.26 +	      
    1.27 +import BFIFO;
    1.28 +	    
    1.29 +import ¶Clocks®¶;
    1.30 +		
    1.31 +import ¶DiniPCIE®¶;
    1.32 +		  
    1.33 +import ¶ListN®¶;
    1.34 +	       
    1.35 +import ¶ModuleContextCore®¶;
    1.36 +			   
    1.37 +import ¶ModuleContext®¶;
    1.38 +		       
    1.39 +import ¶Monad®¶;
    1.40 +	       
    1.41 +import ¶PrimArray®¶;
    1.42 +		   
    1.43 +import ¶RWire®¶;
    1.44 +	       
    1.45 +import ¶RegFile®¶;
    1.46 +		 
    1.47 +import ¶Real®¶;
    1.48 +	      
    1.49 +import ¶RevertingVirtualReg®¶;
    1.50 +			     
    1.51 +import ¶Reserved®¶;
    1.52 +		  
    1.53 +import SFIFO;
    1.54 +	    
    1.55 +import ¶Vector®¶;
    1.56 +		
    1.57 +import ¶BRAMCore®¶;
    1.58 +		  
    1.59 +import ¶BUtils®¶;
    1.60 +		
    1.61 +import ¶Connectable®¶;
    1.62 +		     
    1.63 +import ¶DefaultValue®¶;
    1.64 +		      
    1.65 +import ¶Gearbox®¶;
    1.66 +		 
    1.67 +import ¶GetPut®¶;
    1.68 +		
    1.69 +import ¶AlignedFIFOs®¶;
    1.70 +		      
    1.71 +import ¶ClientServer®¶;
    1.72 +		      
    1.73 +import ¶FIFOLevel®¶;
    1.74 +		   
    1.75 +import ¶SceMiDefines®¶;
    1.76 +		      
    1.77 +import ¶SceMiProxies®¶;
    1.78 +		      
    1.79 +import ¶SpecialFIFOs®¶;
    1.80 +		      
    1.81 +import ¶SceMiInternals®¶;
    1.82 +			
    1.83 +import ¶SceMiAldecMacros®¶;
    1.84 +			  
    1.85 +import ¶SceMiEveMacros®¶;
    1.86 +			
    1.87 +import ¶SceMiMacros®¶;
    1.88 +		     
    1.89 +import ¶TieOff®¶;
    1.90 +		
    1.91 +import Trace;
    1.92 +	    
    1.93 +import MemTypes;
    1.94 +	       
    1.95 +import MemArb;
    1.96 +	     
    1.97 +import ProcTypes;
    1.98 +		
    1.99 +import BRegFile;
   1.100 +	       
   1.101 +import BranchPred;
   1.102 +		 
   1.103 +import DataCacheBlocking;
   1.104 +			
   1.105 +import InstCacheBlocking;
   1.106 +			
   1.107 +import Processor;
   1.108 +		
   1.109 +import Core;
   1.110 +	   
   1.111 +import ¶UnitAppendList®¶;
   1.112 +			
   1.113 +import ¶XilinxCells®¶;
   1.114 +		     
   1.115 +import ¶SceMiClocks®¶;
   1.116 +		     
   1.117 +import ¶SceMiDiniPCIE®¶;
   1.118 +		       
   1.119 +import ¶SceMiTCP®¶;
   1.120 +		  
   1.121 +import ¶XilinxPCIE®¶;
   1.122 +		    
   1.123 +import ¶SceMiVirtex5PCIE®¶;
   1.124 +			  
   1.125 +import ¶SceMiPCIE®¶;
   1.126 +		   
   1.127 +import ¶SceMiCore®¶;
   1.128 +		   
   1.129 +import ¶SceMiXactors®¶;
   1.130 +		      
   1.131 +import ¶SceMiSerialProbe®¶;
   1.132 +			  
   1.133 +import ¶SceMi®¶;
   1.134 +	       
   1.135 +import SceMiLayer;
   1.136 +		 
   1.137 +Bridge.lt :: ¶SceMiDefines®¶.¶SceMiLinkType®¶;
   1.138 +					     
   1.139 +Bridge.mkBridge :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ ¶Prelude®¶.¶Empty®¶
   1.140 +}