1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/core/scemi/SceMiLayer.bsv	Tue Apr 13 17:34:33 2010 -0400
     1.3 @@ -0,0 +1,150 @@
     1.4 +
     1.5 +import ClientServer::*;
     1.6 +import FIFO::*;
     1.7 +import GetPut::*;
     1.8 +import DefaultValue::*;
     1.9 +import SceMi::*;
    1.10 +import Clocks::*;
    1.11 +
    1.12 +import Core::*;
    1.13 +import ProcTypes::*;
    1.14 +import Processor::*;
    1.15 +import DataCacheBlocking::*;
    1.16 +import InstCacheBlocking::*;
    1.17 +
    1.18 +interface DutWrapper;
    1.19 +    interface Core core;
    1.20 +
    1.21 +    // We use a Bit#(1) instead of void because Bluespec Sce-Mi doesn't appear
    1.22 +    // to support sending void over the PCIe link yet.
    1.23 +    interface Put#(Bit#(1)) doreset;
    1.24 +endinterface
    1.25 +
    1.26 +(* synthesize *)
    1.27 +module [Module] mkDutWrapper (DutWrapper);
    1.28 +
    1.29 +    Clock clk <- exposeCurrentClock;
    1.30 +    MakeResetIfc myrst <- mkReset(2000, True, clk);
    1.31 +
    1.32 +    Core coreifc <- mkCore(reset_by myrst.new_rst);
    1.33 +
    1.34 +    // For tracing
    1.35 +    Reg#(int) cycle <- mkReg(0);
    1.36 +    rule printCycles;
    1.37 +        cycle <= cycle + 1;
    1.38 +        $fdisplay(stderr, " => Cycle = %d", cycle);
    1.39 +    endrule
    1.40 +
    1.41 +    interface Core core = coreifc;
    1.42 +
    1.43 +    interface Put doreset;
    1.44 +        method Action put(Bit#(1) x);
    1.45 +            cycle <= 0;
    1.46 +            myrst.assertReset();
    1.47 +        endmethod
    1.48 +    endinterface
    1.49 +    
    1.50 +endmodule
    1.51 +
    1.52 +module [SceMiModule] mkSceMiLayer();
    1.53 +
    1.54 +    SceMiClockConfiguration conf = defaultValue;
    1.55 +
    1.56 +    SceMiClockPortIfc clk_port <- mkSceMiClockPort(conf);
    1.57 +    DutWrapper dut <- buildDut(mkDutWrapper, clk_port);
    1.58 +
    1.59 +    Empty mmem <- mkClientXactor(dut.core.mmem_client, clk_port);
    1.60 +    Empty tohost <- mkCPUToHostXactor(dut.core.tohost, clk_port);
    1.61 +    Empty stats <- mkCoreStatsXactor(dut.core.stats, clk_port);
    1.62 +    Empty doreset <- mkPutXactor(dut.doreset, clk_port);
    1.63 +
    1.64 +    Empty shutdown <- mkShutdownXactor();
    1.65 +
    1.66 +endmodule
    1.67 +
    1.68 +module [SceMiModule] mkCPUToHostXactor#(CPUToHost tohost, SceMiClockPortIfc clk_port ) (Empty);
    1.69 +
    1.70 +    // Access the controlled clock and reset
    1.71 +    Clock cclock = clk_port.cclock;
    1.72 +    Reset creset = clk_port.creset;
    1.73 +
    1.74 +    // req belongs entirely to the controlled clock domain. We'll use the
    1.75 +    // clock domain crossings already implemented by the Bluespec people (in
    1.76 +    // the Put and Get transactors), because they know about such things
    1.77 +    // better than I do.
    1.78 +    FIFO#(int) req <- mkFIFO(clocked_by cclock, reset_by creset);
    1.79 +
    1.80 +    Get#(Bit#(32)) resp = interface Get;
    1.81 +        method ActionValue#(Bit#(32)) get();
    1.82 +            req.deq();
    1.83 +            return tohost.cpuToHost(req.first());
    1.84 +        endmethod
    1.85 +    endinterface;
    1.86 +
    1.87 +    Empty request <- mkPutXactor(toPut(req), clk_port);
    1.88 +    Empty response <- mkGetXactor(resp, clk_port);
    1.89 +
    1.90 +endmodule
    1.91 +
    1.92 +typedef enum {
    1.93 +    DCACHE_ACCESSES, DCACHE_MISSES, DCACHE_WRITEBACKS,
    1.94 +    ICACHE_ACCESSES, ICACHE_MISSES, ICACHE_EVICTIONS,
    1.95 +    PROC_INST, PROC_CYCLES
    1.96 +} StatID deriving(Bits, Eq);
    1.97 +
    1.98 +module [SceMiModule] mkCoreStatsXactor#(CoreStats stats, SceMiClockPortIfc clk_port) (Empty);
    1.99 +
   1.100 +    // Access the controlled clock and reset
   1.101 +    Clock cclock = clk_port.cclock;
   1.102 +    Reset creset = clk_port.creset;
   1.103 +
   1.104 +    // Again, req and resp belong to the controlled clock domain.
   1.105 +    FIFO#(StatID) req <- mkFIFO(clocked_by cclock, reset_by creset);
   1.106 +    FIFO#(Stat) resp <- mkFIFO(clocked_by cclock, reset_by creset);
   1.107 +
   1.108 +    rule handleRequest (True);
   1.109 +        case (req.first())
   1.110 +            DCACHE_ACCESSES: begin
   1.111 +                let x <- stats.dcache.num_accesses.get();
   1.112 +                resp.enq(x);
   1.113 +            end
   1.114 +            DCACHE_MISSES: begin
   1.115 +                let x <- stats.dcache.num_misses.get();
   1.116 +                resp.enq(x);
   1.117 +            end
   1.118 +            DCACHE_WRITEBACKS: begin
   1.119 +                let x <- stats.dcache.num_writebacks.get();
   1.120 +                resp.enq(x);
   1.121 +            end
   1.122 +            ICACHE_ACCESSES: begin
   1.123 +                let x <- stats.icache.num_accesses.get();
   1.124 +                resp.enq(x);
   1.125 +            end
   1.126 +            ICACHE_MISSES: begin
   1.127 +                let x <- stats.icache.num_misses.get();
   1.128 +                resp.enq(x);
   1.129 +            end
   1.130 +            ICACHE_EVICTIONS: begin
   1.131 +                let x <- stats.icache.num_evictions.get();
   1.132 +                resp.enq(x);
   1.133 +            end
   1.134 +            PROC_INST: begin
   1.135 +                let x <- stats.proc.num_inst.get();
   1.136 +                resp.enq(x);
   1.137 +            end
   1.138 +            PROC_CYCLES: begin
   1.139 +                let x <- stats.proc.num_cycles.get();
   1.140 +                resp.enq(x);
   1.141 +            end
   1.142 +        endcase
   1.143 +        req.deq();
   1.144 +    endrule
   1.145 +
   1.146 +    Server#(StatID, Stat) server = interface Server;
   1.147 +        interface Get response = toGet(resp);
   1.148 +        interface Put request = toPut(req);
   1.149 +    endinterface;
   1.150 +
   1.151 +    Empty xx <- mkServerXactor(server, clk_port);
   1.152 +endmodule
   1.153 +