1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/modules/bluespec/Pygar/core/#olCore.bsv#	Tue Apr 27 09:03:28 2010 -0400
     1.3 @@ -0,0 +1,90 @@
     1.4 +// The MIT License
     1.5 +
     1.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
     1.7 +
     1.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
     1.9 +// of this software and associated documentation files (the "Software"), to deal
    1.10 +// in the Software without restriction, including without limitation the rights
    1.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    1.12 +// copies of the Software, and to permit persons to whom the Software is
    1.13 +// furnished to do so, subject to the following conditions:
    1.14 +
    1.15 +// The above copyright notice and this permission notice shall be included in
    1.16 +// all copies or substantial portions of the Software.
    1.17 +
    1.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    1.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    1.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    1.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    1.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    1.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    1.24 +// THE SOFTWARE.
    1.25 +
    1.26 +import Connectable::*;
    1.27 +import GetPut::*;
    1.28 +import ClientServer::*;
    1.29 +
    1.30 +
    1.31 +import DataCacheBlocking::*;
    1.32 +import InstCacheBlocking::*;
    1.33 +import Processor::*;
    1.34 +import MemArb::*;
    1.35 +import MemTypes::*;
    1.36 +
    1.37 +`include "asim/provides/data_cache.bsh"
    1.38 +`include "asim/provides/instruction_cache.bsh"
    1.39 +
    1.40 +interface CoreStats;
    1.41 +  interface DCacheStats dcache;
    1.42 +  interface ICacheStats icache;
    1.43 +  interface ProcStats proc;
    1.44 +endinterface
    1.45 +
    1.46 +interface Core;
    1.47 +
    1.48 +  // Interface from core to main memory
    1.49 +  interface Client#(MainMemReq,MainMemResp) mmem_client;
    1.50 +
    1.51 +  // Statistics
    1.52 +  interface CoreStats stats;
    1.53 +
    1.54 +  // CPU to Host
    1.55 +  interface CPUToHost tohost;
    1.56 +
    1.57 +  // Interface to Audio Pipeline
    1.58 +  interface Audio audio;
    1.59 +
    1.60 +endinterface
    1.61 +
    1.62 +(* synthesize *)
    1.63 +module mkCore(Core);
    1.64 +
    1.65 +  // Instantiate the modules
    1.66 +  Proc proc <- mkProc();
    1.67 +  ICache#(InstReq,InstResp) icache <- mkInstCache();
    1.68 +  DCache#(DataReq,DataResp) dcache <- mkDataCache();
    1.69 +  MemArb marb <- mkMemArb();
    1.70 +
    1.71 +  // Internal connections
    1.72 +  mkConnection( proc.statsEn_get,   icache.statsEn_put );
    1.73 +  mkConnection( proc.statsEn_get,   dcache.statsEn_put );
    1.74 +  mkConnection( proc.imem_client,   icache.proc_server );
    1.75 +  mkConnection( proc.dmem_client,   dcache.proc_server );
    1.76 +  mkConnection( icache.mmem_client, marb.cache0_server );
    1.77 +  mkConnection( dcache.mmem_client, marb.cache1_server );
    1.78 +
    1.79 +  // Methods
    1.80 +  interface mmem_client = marb.mmem_client;
    1.81 +
    1.82 +  interface CoreStats stats;
    1.83 +    interface dcache = dcache.stats;
    1.84 +    interface icache = icache.stats;
    1.85 +    interface proc = proc.stats;
    1.86 +  endinterface
    1.87 +
    1.88 +  interface CPUToHost tohost = proc.tohost;
    1.89 +
    1.90 +  interface Audio audio = proc.audio;
    1.91 +	
    1.92 +endmodule
    1.93 +