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annotate modules/bluespec/Pygar/core/#olCore.bsv# @ 13:6d461680c6d9 pygar svn.14

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[svn r14] more stuff
author punk
date Tue, 27 Apr 2010 09:03:28 -0400
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punk@13 1 // The MIT License
punk@13 2
punk@13 3 // Copyright (c) 2009 Massachusetts Institute of Technology
punk@13 4
punk@13 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@13 6 // of this software and associated documentation files (the "Software"), to deal
punk@13 7 // in the Software without restriction, including without limitation the rights
punk@13 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@13 9 // copies of the Software, and to permit persons to whom the Software is
punk@13 10 // furnished to do so, subject to the following conditions:
punk@13 11
punk@13 12 // The above copyright notice and this permission notice shall be included in
punk@13 13 // all copies or substantial portions of the Software.
punk@13 14
punk@13 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@13 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@13 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@13 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@13 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@13 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@13 21 // THE SOFTWARE.
punk@13 22
punk@13 23 import Connectable::*;
punk@13 24 import GetPut::*;
punk@13 25 import ClientServer::*;
punk@13 26
punk@13 27
punk@13 28 import DataCacheBlocking::*;
punk@13 29 import InstCacheBlocking::*;
punk@13 30 import Processor::*;
punk@13 31 import MemArb::*;
punk@13 32 import MemTypes::*;
punk@13 33
punk@13 34 `include "asim/provides/data_cache.bsh"
punk@13 35 `include "asim/provides/instruction_cache.bsh"
punk@13 36
punk@13 37 interface CoreStats;
punk@13 38 interface DCacheStats dcache;
punk@13 39 interface ICacheStats icache;
punk@13 40 interface ProcStats proc;
punk@13 41 endinterface
punk@13 42
punk@13 43 interface Core;
punk@13 44
punk@13 45 // Interface from core to main memory
punk@13 46 interface Client#(MainMemReq,MainMemResp) mmem_client;
punk@13 47
punk@13 48 // Statistics
punk@13 49 interface CoreStats stats;
punk@13 50
punk@13 51 // CPU to Host
punk@13 52 interface CPUToHost tohost;
punk@13 53
punk@13 54 // Interface to Audio Pipeline
punk@13 55 interface Audio audio;
punk@13 56
punk@13 57 endinterface
punk@13 58
punk@13 59 (* synthesize *)
punk@13 60 module mkCore(Core);
punk@13 61
punk@13 62 // Instantiate the modules
punk@13 63 Proc proc <- mkProc();
punk@13 64 ICache#(InstReq,InstResp) icache <- mkInstCache();
punk@13 65 DCache#(DataReq,DataResp) dcache <- mkDataCache();
punk@13 66 MemArb marb <- mkMemArb();
punk@13 67
punk@13 68 // Internal connections
punk@13 69 mkConnection( proc.statsEn_get, icache.statsEn_put );
punk@13 70 mkConnection( proc.statsEn_get, dcache.statsEn_put );
punk@13 71 mkConnection( proc.imem_client, icache.proc_server );
punk@13 72 mkConnection( proc.dmem_client, dcache.proc_server );
punk@13 73 mkConnection( icache.mmem_client, marb.cache0_server );
punk@13 74 mkConnection( dcache.mmem_client, marb.cache1_server );
punk@13 75
punk@13 76 // Methods
punk@13 77 interface mmem_client = marb.mmem_client;
punk@13 78
punk@13 79 interface CoreStats stats;
punk@13 80 interface dcache = dcache.stats;
punk@13 81 interface icache = icache.stats;
punk@13 82 interface proc = proc.stats;
punk@13 83 endinterface
punk@13 84
punk@13 85 interface CPUToHost tohost = proc.tohost;
punk@13 86
punk@13 87 interface Audio audio = proc.audio;
punk@13 88
punk@13 89 endmodule
punk@13 90