1.1 --- a/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 13:42:07 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv	Wed May 05 14:40:48 2010 -0400
     1.3 @@ -132,9 +132,10 @@
     1.4  
     1.5    Reg#(Bool)     statsEn        <- mkReg(False);
     1.6  
     1.7 -  STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);
     1.8 -  STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);
     1.9 -  STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);
    1.10 +   //rlm: 
    1.11 +  //STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);
    1.12 +  //STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);
    1.13 +  //STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);
    1.14  
    1.15    //-----------------------------------------------------------
    1.16    // Name some wires
    1.17 @@ -162,9 +163,9 @@
    1.18    rule access ( (stage == Access) && respQ.notFull() );
    1.19  
    1.20      // Statistics
    1.21 -
    1.22 -    if ( statsEn )
    1.23 -      num_accesses.incr();
    1.24 +     //rlm: 
    1.25 +   // if ( statsEn )
    1.26 +     // num_accesses.incr();
    1.27    
    1.28      // Check tag and valid bit to see if this is a hit or a miss
    1.29  
    1.30 @@ -195,11 +196,12 @@
    1.31      else 
    1.32       begin
    1.33         traceTiny("mkInstCacheBlocking", "hitMiss","m");
    1.34 -       if ( statsEn )
    1.35 -         num_misses.incr();
    1.36 -       if ( statsEn )
    1.37 -         if ( isJust(cacheLineTag) )
    1.38 -	   num_evictions.incr();	
    1.39 +       //rlm:
    1.40 +	//if ( statsEn )
    1.41 +         //num_misses.incr();
    1.42 +       //if ( statsEn )
    1.43 +         //if ( isJust(cacheLineTag) )
    1.44 +	   //num_evictions.incr();	
    1.45  
    1.46         MainMemReq rfReq
    1.47          = LoadReq { tag  : 0,