1.1 --- a/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 13:42:07 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv	Wed May 05 14:40:48 2010 -0400
     1.3 @@ -130,10 +130,10 @@
     1.4    // Statistics state
     1.5  
     1.6    Reg#(Bool)     statsEn        <- mkReg(False);
     1.7 -
     1.8 -  STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
     1.9 -  STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
    1.10 -  STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
    1.11 +   //rlm: 
    1.12 +  //STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
    1.13 +  //STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
    1.14 +  //STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
    1.15  
    1.16    //-----------------------------------------------------------
    1.17    // Name some wires
    1.18 @@ -160,9 +160,9 @@
    1.19    rule access ( (stage == Access) && respQ.notFull() );
    1.20  
    1.21      // Statistics
    1.22 -
    1.23 -    if ( statsEn )
    1.24 -       num_accesses.incr();
    1.25 +     //rlm: 
    1.26 +    //if ( statsEn )
    1.27 +      // num_accesses.incr();
    1.28   
    1.29  
    1.30      // Get the corresponding tag from the rams
    1.31 @@ -196,16 +196,17 @@
    1.32      else 
    1.33        begin
    1.34          traceTiny("mkDataCacheBlocking", "hitMiss","m");
    1.35 -        if ( statsEn )
    1.36 -          num_misses.incr();
    1.37 +         //rlm: 
    1.38 +	 //if ( statsEn )
    1.39 +         // num_misses.incr();
    1.40  
    1.41          // Currently we don't use dirty bits so we always writeback the data if it is valid
    1.42  
    1.43          if ( isValid(cacheLineTag) )
    1.44           begin
    1.45 -
    1.46 -           if ( statsEn )
    1.47 -             num_writebacks.incr();
    1.48 +	    //rlm: 
    1.49 +          // if ( statsEn )
    1.50 +            // num_writebacks.incr();
    1.51  
    1.52  	   MainMemReq wbReq 
    1.53  	    = StoreReq { tag  : 0,