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comparison modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv @ 49:61f6267cb3db pygar svn.50

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[svn r50] removed problematic stats stuff
author rlm
date Wed, 05 May 2010 14:40:48 -0400
parents 3958de09a7c1
children 9fe5ed4af92d
comparison
equal deleted inserted replaced
48:a139cc07b773 49:61f6267cb3db
128 Reg#(CacheLineIndex) initCounter <- mkReg(1); 128 Reg#(CacheLineIndex) initCounter <- mkReg(1);
129 129
130 // Statistics state 130 // Statistics state
131 131
132 Reg#(Bool) statsEn <- mkReg(False); 132 Reg#(Bool) statsEn <- mkReg(False);
133 133 //rlm:
134 STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES); 134 //STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
135 STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES); 135 //STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
136 STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS); 136 //STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
137 137
138 //----------------------------------------------------------- 138 //-----------------------------------------------------------
139 // Name some wires 139 // Name some wires
140 140
141 let req = reqQ.first(); 141 let req = reqQ.first();
158 // Access cache rule 158 // Access cache rule
159 159
160 rule access ( (stage == Access) && respQ.notFull() ); 160 rule access ( (stage == Access) && respQ.notFull() );
161 161
162 // Statistics 162 // Statistics
163 163 //rlm:
164 if ( statsEn ) 164 //if ( statsEn )
165 num_accesses.incr(); 165 // num_accesses.incr();
166 166
167 167
168 // Get the corresponding tag from the rams 168 // Get the corresponding tag from the rams
169 169
170 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); 170 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
194 // Handle cache misses ... 194 // Handle cache misses ...
195 195
196 else 196 else
197 begin 197 begin
198 traceTiny("mkDataCacheBlocking", "hitMiss","m"); 198 traceTiny("mkDataCacheBlocking", "hitMiss","m");
199 if ( statsEn ) 199 //rlm:
200 num_misses.incr(); 200 //if ( statsEn )
201 // num_misses.incr();
201 202
202 // Currently we don't use dirty bits so we always writeback the data if it is valid 203 // Currently we don't use dirty bits so we always writeback the data if it is valid
203 204
204 if ( isValid(cacheLineTag) ) 205 if ( isValid(cacheLineTag) )
205 begin 206 begin
206 207 //rlm:
207 if ( statsEn ) 208 // if ( statsEn )
208 num_writebacks.incr(); 209 // num_writebacks.incr();
209 210
210 MainMemReq wbReq 211 MainMemReq wbReq
211 = StoreReq { tag : 0, 212 = StoreReq { tag : 0,
212 addr : { unJust(cacheLineTag), reqIndex, 2'b0 }, 213 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },
213 data : cacheDataRam.sub(reqIndex) }; 214 data : cacheDataRam.sub(reqIndex) };