Mercurial > pygar

diff modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 43:4d87fa55a776 pygar svn.44

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[svn r44] processor largely working and mixer in good status
author punk
date Wed, 05 May 2010 12:28:07 -0400
parents ced2ebd41347
children 97d1959f7c5c
line wrap: on
line diff
     1.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 01:09:09 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Wed May 05 12:28:07 2010 -0400
     1.3 @@ -37,7 +37,7 @@
     1.4  `include "asim/provides/audio_pipe_types.bsh"  //provides Audio Pipeline interface
     1.5  `include "asim/provides/path_types.bsh"
     1.6  `include "asim/provides/core.bsh"
     1.7 -//`include "asim/provides/mixer.bsh"
     1.8 +`include "asim/provides/mixer.bsh"
     1.9  `include "asim/provides/processor_library.bsh"
    1.10  `include "asim/provides/fpga_components.bsh"
    1.11  `include "asim/provides/scratchpad_memory.bsh"
    1.12 @@ -79,13 +79,13 @@
    1.13      let coreReq <- core.mmem_client.request.get;
    1.14      case (coreReq) matches 
    1.15        tagged LoadReq .load: begin
    1.16 -	                      $display("PIPE Load Addr Req %x", load.addr); 
    1.17 +//	                      $display("PIPE Load Addr Req %h", load.addr); 
    1.18                                //Allocate ROB space
    1.19                                memory.readReq(truncate(load.addr>>2));
    1.20                                tags.enq(load.tag);
    1.21                              end
    1.22         tagged StoreReq .store: begin
    1.23 -	  	              $display("PIPE Write Addr Req %x", store.addr); 
    1.24 +//	  	              $display("PIPE Write Addr Req %h", store.addr); 
    1.25  	                      memory.write(truncate(store.addr>>2),store.data);
    1.26                                end
    1.27      endcase
    1.28 @@ -96,7 +96,7 @@
    1.29      tags.deq;
    1.30      core.mmem_client.response.put(tagged LoadResp {data:memResp,
    1.31                                                     tag: tags.first});
    1.32 -     	                $display("PIPE Receive MemReq %x", memResp); 
    1.33 +//   	                $display("PIPE Receive MemReq %x", memResp); 
    1.34    endrule
    1.35  
    1.36     rule feedOutput;
    1.37 @@ -131,13 +131,13 @@
    1.38  
    1.39        if(ctrl == EndOfFile)
    1.40  	begin
    1.41 -	  $display("lsp: PROCESSOR received EOF   ");
    1.42 -          core.sampleInput.put(tagged EndOfFile);
    1.43 +	   $display("lsp: PIPE received EOF   ");
    1.44 +           core.sampleInput.put(tagged EndOfFile);
    1.45         end
    1.46       else 
    1.47  	begin
    1.48 -	  $display("lsp: PROCESSOR received Data   ");
    1.49 -          core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));
    1.50 +//	   $display("lsp: PIPE received Data   ");
    1.51 +           core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));
    1.52         end
    1.53     endrule     
    1.54  endmodule