1.1 --- a/modules/bluespec/Pygar/core/Processor.bsv	Tue May 11 23:23:21 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/Processor.bsv	Wed May 12 00:06:05 2010 -0400
     1.3 @@ -37,7 +37,6 @@
     1.4  import ProcTypes::*;
     1.5  import BRegFile::*;
     1.6  import BranchPred::*;
     1.7 -//import PathTypes::*;  This is only there to force the debugging
     1.8  
     1.9  //AWB includes
    1.10  `include "asim/provides/low_level_platform_interface.bsh"
    1.11 @@ -57,6 +56,7 @@
    1.12  // pipeline
    1.13  
    1.14  `include "asim/provides/audio_pipe_types.bsh"
    1.15 +`include "asim/provides/path_types.bsh"
    1.16  
    1.17  //interface CPUToHost;
    1.18  //  method Bit#(32) cpuToHost(int req);
    1.19 @@ -71,12 +71,12 @@
    1.20    // Interface for enabling/disabling statistics on the rest of the core
    1.21    interface Get#(Bool) statsEn_get;
    1.22  
    1.23 -//  // Interface to host
    1.24 -//  interface CPUToHost tohost;
    1.25 +  // Interface to host
    1.26 +  interface Get#(Bit#(32)) pcCount;
    1.27  
    1.28    // Interface to Audio Pipeline
    1.29 -  interface Get#(AudioProcessorUnit) sampleOutput;
    1.30 -  interface Put#(AudioProcessorUnit) sampleInput;
    1.31 +  interface Get#(AudioStream) sampleOutput;
    1.32 +  interface Put#(AudioStream) sampleInput;
    1.33  	
    1.34  endinterface
    1.35  
    1.36 @@ -179,6 +179,8 @@
    1.37  
    1.38      endcase
    1.39  endfunction
    1.40 +
    1.41 +
    1.42  //-----------------------------------------------------------
    1.43  // Reference processor
    1.44  //-----------------------------------------------------------
    1.45 @@ -213,6 +215,9 @@
    1.46     Reg#(Bool)     cp0_statsEn  <- mkReg(False);
    1.47     Reg#(Bool)     cp0_audioEOF <- mkReg(False);  // Register to let code that EOF is reached
    1.48     Reg#(Bool)     cp0_progComp <- mkReg(False);  // Register to let processor know that the program is complete (as this terminates)
    1.49 + 
    1.50 +   Reg#(Bool)     code_bypass  <- mkReg(True);   // Register to enable passing invalid packets once all valid ones are passed OUT 
    1.51 +                                                 // (this becomes false at first valid packet) 
    1.52      
    1.53     // Memory request/response state
    1.54     
    1.55 @@ -223,9 +228,9 @@
    1.56     FIFO#(DataResp) dataRespQ   <- mkFIFO();
    1.57  
    1.58     // Audio I/O
    1.59 -   FIFO#(AudioProcessorUnit) inAudioFifo <- mkSizedFIFO(512);
    1.60 -   FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
    1.61 -
    1.62 +   FIFO#(AudioStream) inAudioFifo  <- mkSizedFIFO(512);
    1.63 +   FIFO#(AudioStream) outAudioFifo <- mkFIFO;
    1.64 +   Reg#(VoiceId)      channel      <-mkReg(0);  // Set based on the reading the incoming data.  Not entirely sure I like this.  What if the program generates samples?
    1.65  
    1.66     // Statistics state (2010)
    1.67     //   Reg#(Stat) num_cycles <- mkReg(0);
    1.68 @@ -239,6 +244,20 @@
    1.69     //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
    1.70  
    1.71     //-----------------------------------------------------------
    1.72 +   // Internal Functions
    1.73 +
    1.74 +   function Bool stallMTCO_MFCO(Instr inst);
    1.75 +      case(inst) matches
    1.76 +	 tagged MTC0 .it : 
    1.77 +	    begin
    1.78 +	       case (it.cop0dst)
    1.79 +		  5'd26 : return cp0_progComp;  // If true, processor service sendEnd which clears it.
    1.80 +	       endcase
    1.81 +	    end
    1.82 +      endcase					
    1.83 +   endfunction
    1.84 +   
    1.85 +   //-----------------------------------------------------------
    1.86     // Rules
    1.87  
    1.88     (* descending_urgency = "exec, pcgen" *)
    1.89 @@ -273,7 +292,8 @@
    1.90     rule exec (instRespQ.first() matches tagged LoadResp.ld
    1.91  	      &&& (ld.tag == epoch)
    1.92  	      &&& unpack(ld.data) matches .inst
    1.93 -              &&& !stall(inst, wbQ));
    1.94 +              &&& !stall(inst, wbQ)
    1.95 +	      &&& !stallMTCO_MFCO(inst));
    1.96  
    1.97        // Some abbreviations
    1.98        let sext = signExtend;
    1.99 @@ -301,6 +321,7 @@
   1.100        traceTiny("mkProc", "exInstTiny",inst);
   1.101        traceFull("mkProc", "exInstFull",inst);
   1.102  
   1.103 +//      $display("PROCESSOR: Exec Fires");
   1.104        case ( inst ) matches
   1.105  
   1.106  	 // -- Memory Ops ------------------------------------------------      
   1.107 @@ -553,7 +574,8 @@
   1.108  	       5'd10 : cp0_statsEn <= unpack(truncate(val_rsrc1));
   1.109  	       5'd21 : cp0_tohost  <= truncate(val_rsrc1);
   1.110  	       5'd26 : cp0_progComp <= unpack(truncate(val_rsrc1)); //states audio program completed and termination okay
   1.111 - 	       5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(val_rsrc1)));  //Bit size is 16 not 32 
   1.112 + 	       5'd27 : outAudioFifo.enq(AudioStream {voice: channel, data: tagged Valid
   1.113 +									   tagged Sample unpack(truncate(val_rsrc1)) });  //Bit size is 16 not 32
   1.114  	       default :
   1.115  	       $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
   1.116  	    endcase
   1.117 @@ -569,26 +591,35 @@
   1.118                 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
   1.119                 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost   });
   1.120  	       5'd25 : begin
   1.121 -//			  $display( "**** EOF Requested");
   1.122 -			  let sample = inAudioFifo.first();
   1.123 -			  case (sample) matches
   1.124 -			     tagged EndOfFile :
   1.125 -				begin
   1.126 -				   $display("PROCESSOR sent toC EOF");
   1.127 -				   wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(True)) });  // Reading clears bit
   1.128 -				   inAudioFifo.deq;
   1.129 -			        end
   1.130 -			     tagged Sample .data:
   1.131 -				   wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(False)) });  // Reading clears bit
   1.132 -			  endcase
   1.133 +//			  $display( "**** EOF Requested\n ");  //Should never run if inAudioFifo.first not valid
   1.134 +			  let stream = inAudioFifo.first();
   1.135 +			  if (stream.data matches tagged Valid .sample)
   1.136 +			    begin
   1.137 +			       case (sample) matches
   1.138 +				  tagged EndOfFile :
   1.139 +				     begin
   1.140 +					$display("PROCESSOR sent toC EOF");
   1.141 +					wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(True)) });  // Reading clears bit
   1.142 +					inAudioFifo.deq;
   1.143 +			              end
   1.144 +				   tagged Sample .audio:
   1.145 +				      wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(False)) });  // Reading clears bit
   1.146 +			       endcase
   1.147 +			       code_bypass <= False;
   1.148 +			    end
   1.149 +			  else $display("PROCESSOR code trying to read Invalid Audio Stream");
   1.150  		       end
   1.151  	       5'd28 : begin
   1.152  			  $display( "***** Reqesting Sample");
   1.153 -			  let sample = inAudioFifo.first();        // is this going to cause perf. delay?
   1.154 -			  if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF  
   1.155 -	     		     wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) });  // do I need pack?
   1.156 -			  else $display ( "Audio File EOF Reached.  Invalid sample request.");
   1.157 -			  inAudioFifo.deq();
   1.158 +			  let stream = inAudioFifo.first();        // is this going to cause perf. delay?
   1.159 +			  if (stream.data matches tagged Valid .sample)
   1.160 +			    begin			  
   1.161 +			       if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF  
   1.162 +	     			 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) });  // do I need pack?
   1.163 +			       else $display ( "Audio File EOF Reached.  Invalid sample request.");
   1.164 +			       inAudioFifo.deq();
   1.165 +			    end
   1.166 +			  else $display("PROCESSOR code trying to read Invalid Audio Stream");
   1.167  		       end
   1.168                default : 
   1.169                  $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
   1.170 @@ -645,14 +676,13 @@
   1.171   //     num_cycles.incr();
   1.172   // endrule
   1.173  
   1.174 -/*
   1.175 - // for now, we don't do anything.
   1.176 -  rule connectAudioReqResp;
   1.177 -    $display("rlm: PROCESSOR copies a datum\n");
   1.178 +  rule bypass (code_bypass &&& 
   1.179 +	      !cp0_progComp &&&   //never fires at the same time as sendEnd where it is enabled
   1.180 +              inAudioFifo.first().data matches tagged Invalid) ;
   1.181      outAudioFifo.enq(inAudioFifo.first());
   1.182      inAudioFifo.deq;
   1.183    endrule
   1.184 -*/
   1.185 +
   1.186  /*
   1.187    rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
   1.188       $display (" PROCESSOR End Audio Flag Set ");
   1.189 @@ -660,10 +690,12 @@
   1.190       inAudioFifo.deq;
   1.191    endrule
   1.192  */
   1.193 +  (* descending_urgency = "sendProcEnd, exec" *)
   1.194    rule sendProcEnd (cp0_progComp);
   1.195       $display (" PROCESSOR Says Program Complete ");
   1.196 -     outAudioFifo.enq(tagged EndOfFile);
   1.197 -     cp0_progComp <= False;  //only send one.  And functions to reset
   1.198 +     outAudioFifo.enq(AudioStream {voice: channel, data: tagged Valid tagged EndOfFile });  //  Only send one
   1.199 +     cp0_progComp <= False;               //  And functions to reset
   1.200 +     code_bypass <= True;                 //  Enable Bypass so that invalids get thru
   1.201    endrule
   1.202  
   1.203     
   1.204 @@ -696,6 +728,7 @@
   1.205     
   1.206    interface Get sampleOutput = fifoToGet(outAudioFifo);
   1.207    interface Put sampleInput = fifoToPut(inAudioFifo);
   1.208 +  interface Get pcCount = toGet(asReg(pc));
   1.209  
   1.210  endmodule
   1.211