1.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Mon May 03 09:53:56 2010 -0400
     1.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Tue May 04 10:13:53 2010 -0400
     1.3 @@ -35,9 +35,14 @@
     1.4  
     1.5  //Local includes
     1.6  `include "asim/provides/audio_pipe_types.bsh"  //provides Audio Pipeline interface
     1.7 +`include "asim/provides/path_types.bsh"
     1.8  `include "asim/provides/core.bsh"
     1.9  `include "asim/provides/processor_library.bsh"
    1.10  `include "asim/provides/fpga_components.bsh"
    1.11 +`include "asim/provides/scratchpad_memory.bsh"
    1.12 +`include "asim/provides/mem_services.bsh"
    1.13 +`include "asim/dict/VDEV_SCRATCH.bsh"
    1.14 +
    1.15  `include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
    1.16  //`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
    1.17  
    1.18 @@ -47,7 +52,10 @@
    1.19  
    1.20    //External memory 
    1.21    // I'm not comfortable assuming that the memory subsystem is in order  
    1.22 -  // So I'll insert a completion buffer here.  
    1.23 +  // So I'll insert a completion buffer here.
    1.24 +  MEMORY_IFC#(Bit#(18), Bit#(32)) memory <- mkScratchpad(`VDEV_SCRATCH_MEMORY, SCRATCHPAD_CACHED);   //Services Memory items
    1.25 +
    1.26 +  // Services Samples 
    1.27    ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR();   
    1.28    // Make this big enough so that several outstanding requests may be supported
    1.29    FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
    1.30 @@ -63,24 +71,22 @@
    1.31      case (coreReq) matches 
    1.32        tagged LoadReq .load: begin
    1.33                                //Allocate ROB space
    1.34 -                              client_stub.makeRequest_MemoryRequestLoad(load.addr);
    1.35 +                              memory.readReq(truncate(load.addr>>2));
    1.36                                tags.enq(load.tag);
    1.37                              end
    1.38        tagged StoreReq .store: begin
    1.39 -                                client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
    1.40 +	                      memory.write(truncate(store.addr>>2),store.data);
    1.41                                end
    1.42      endcase
    1.43    endrule
    1.44    
    1.45    rule receiveMemResp;
    1.46 -    let memResp <- client_stub.getResponse_MemoryRequestLoad();
    1.47 +    let memResp <- memory.readRsp();
    1.48      tags.deq;
    1.49      core.mmem_client.response.put(tagged LoadResp {data:memResp,
    1.50                                                     tag: tags.first});
    1.51    endrule
    1.52  
    1.53 -  // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together.
    1.54 -
    1.55     rule feedOutput;
    1.56       let pipelineData <- core.sampleOutput.get();
    1.57       AudioProcessorControl endOfFileTag = EndOfFile;