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comparison modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv @ 63:1d5cbb5343d2 pygar svn.64

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[svn r64] mods to compile correctly for FPGA
author punk
date Mon, 10 May 2010 22:54:54 -0400
parents 6179c07c21d7
children
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62:90fa9b289aab 63:1d5cbb5343d2
109 // Main module 109 // Main module
110 //---------------------------------------------------------------------- 110 //----------------------------------------------------------------------
111 111
112 (* doc = "synthesis attribute ram_style mkInstCache distributed;" *) 112 (* doc = "synthesis attribute ram_style mkInstCache distributed;" *)
113 (* synthesize *) 113 (* synthesize *)
114 module [CONNECTED_MODULE] mkInstCache( ICache#(InstReq,InstResp) ); 114 module mkInstCache( ICache#(InstReq,InstResp) );
115 115
116 //----------------------------------------------------------- 116 //-----------------------------------------------------------
117 // State 117 // State
118 118
119 Reg#(CacheStage) stage <- mkReg(Init); 119 Reg#(CacheStage) stage <- mkReg(Init);