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comparison modules/bluespec/Pygar/lab4/DataCacheBlocking.bsv @ 63:1d5cbb5343d2 pygar svn.64

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[svn r64] mods to compile correctly for FPGA
author punk
date Mon, 10 May 2010 22:54:54 -0400
parents 6179c07c21d7
children
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62:90fa9b289aab 63:1d5cbb5343d2
108 // Main module 108 // Main module
109 //---------------------------------------------------------------------- 109 //----------------------------------------------------------------------
110 110
111 (* doc = "synthesis attribute ram_style mkDataCache distributed;" *) 111 (* doc = "synthesis attribute ram_style mkDataCache distributed;" *)
112 (* synthesize *) 112 (* synthesize *)
113 module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) ); 113 module mkDataCache( DCache#(DataReq,DataResp) );
114 114
115 //----------------------------------------------------------- 115 //-----------------------------------------------------------
116 // State 116 // State
117 117
118 Reg#(CacheStage) stage <- mkReg(Init); 118 Reg#(CacheStage) stage <- mkReg(Init);