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comparison modules/bluespec/Pygar/core/#Processor.bsv# @ 26:f5dfbe28fa59 pygar svn.27

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[svn r27] Fixed Instruction trace issue.
author punk
date Fri, 30 Apr 2010 09:03:10 -0400
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children 99519a031813
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25:220c14f5963c 26:f5dfbe28fa59
1 /// The MIT License
2
3 // Copyright (c) 2009 Massachusetts Institute of Technology
4
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
11
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
14
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
22
23
24 import Connectable::*;
25 import GetPut::*;
26 import ClientServer::*;
27 import RegFile::*;
28
29 import FIFO::*;
30 import FIFOF::*;
31 import SFIFO::*;
32 import RWire::*;
33 import Trace::*;
34 import BFIFO::*;
35 import ProcTypes::*;
36 import BRegFile::*;
37 import BranchPred::*;
38 //import PathTypes::*; This is only there to force the debugging
39
40 //AWB includes
41 `include "asim/provides/low_level_platform_interface.bsh"
42 `include "asim/provides/soft_connections.bsh"
43 `include "asim/provides/common_services.bsh"
44
45 // Local includes
46 //`include "asim/provides/processor_library.bsh" (included above directly)
47 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
48 `include "asim/provides/common_services.bsh"
49 `include "asim/dict/STATS_PROCESSOR.bsh"
50 `include "asim/provides/processor_library.bsh"
51
52 // Local includes. Look for the correspondingly named .awb files
53 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
54 // to find the actual Bluespec files which are used to generate
55 // these includes. These files are specific to this audio processing
56 // pipeline
57
58 `include "asim/provides/audio_pipe_types.bsh"
59
60 //interface CPUToHost;
61 // method Bit#(32) cpuToHost(int req);
62 //endinterface
63
64 interface Proc;
65
66 // Interface from processor to caches
67 interface Client#(DataReq,DataResp) dmem_client;
68 interface Client#(InstReq,InstResp) imem_client;
69
70 // Interface for enabling/disabling statistics on the rest of the core
71 interface Get#(Bool) statsEn_get;
72
73 // // Interface to host
74 // interface CPUToHost tohost;
75
76 // Interface to Audio Pipeline
77 interface Get#(AudioProcessorUnit) sampleOutput;
78
79 endinterface
80
81 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
82 //interface AudioOut;
83 // interface Get#(AudioProcessorUnit) audioSampleOutput;
84 //endinterface
85
86 //interface AudioIn;
87 // interface Put#(AudioProcessorUnit) audioSampleInput;
88 //endinterface
89
90 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
91
92 //-----------------------------------------------------------
93 // Register file module
94 //-----------------------------------------------------------
95
96 interface BRFile;
97 method Action wr( Rindx rindx, Bit#(32) data );
98 method Bit#(32) rd1( Rindx rindx );
99 method Bit#(32) rd2( Rindx rindx );
100 endinterface
101
102 module mkBRFile( BRFile );
103
104 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
105
106 method Action wr( Rindx rindx, Bit#(32) data );
107 rfile.upd( rindx, data );
108 endmethod
109
110 method Bit#(32) rd1( Rindx rindx );
111 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
112 endmethod
113
114 method Bit#(32) rd2( Rindx rindx );
115 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
116 endmethod
117
118 endmodule
119
120 //-----------------------------------------------------------
121 // Helper functions
122 //-----------------------------------------------------------
123
124 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
125 return zeroExtend( pack( signedLT(val1,val2) ) );
126 endfunction
127
128 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
129 return zeroExtend( pack( val1 < val2 ) );
130 endfunction
131
132 function Bit#(32) rshft( Bit#(32) val );
133 return zeroExtend(val[4:0]);
134 endfunction
135
136
137 //-----------------------------------------------------------
138 // Find funct for wbQ
139 //-----------------------------------------------------------
140 function Bool findwbf(Rindx fVal, WBResult cmpVal);
141 case (cmpVal) matches
142 tagged WB_ALU {data:.res, dest:.rd} :
143 return (fVal == rd);
144 tagged WB_Load .rd :
145 return (fVal == rd);
146 tagged WB_Store .st :
147 return False;
148 tagged WB_Host .x :
149 return False;
150 endcase
151 endfunction
152
153
154 //-----------------------------------------------------------
155 // Stall funct for wbQ
156 //-----------------------------------------------------------
157 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
158 case (inst) matches
159 // -- Memory Ops ------------------------------------------------
160 tagged LW .it :
161 return f.find(it.rbase);
162 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
163 return (f.find(addr) || f.find2(dreg));
164
165 // -- Simple Ops ------------------------------------------------
166 tagged ADDIU .it : return f.find(it.rsrc);
167 tagged SLTI .it : return f.find(it.rsrc);
168 tagged SLTIU .it : return f.find(it.rsrc);
169 tagged ANDI .it : return f.find(it.rsrc);
170 tagged ORI .it : return f.find(it.rsrc);
171 tagged XORI .it : return f.find(it.rsrc);
172
173 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
174 tagged SLL .it : return f.find(it.rsrc);
175 tagged SRL .it : return f.find(it.rsrc);
176 tagged SRA .it : return f.find(it.rsrc);
177 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
178 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
179 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
180 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
181 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
182 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
183 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
184 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
185 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
186 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
187 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
188
189
190 // -- Branches --------------------------------------------------
191
192 tagged BLEZ .it : return (f.find(it.rsrc));
193 tagged BGTZ .it : return (f.find(it.rsrc));
194 tagged BLTZ .it : return (f.find(it.rsrc));
195 tagged BGEZ .it : return (f.find(it.rsrc));
196 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
197 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
198
199 // -- Jumps -----------------------------------------------------
200
201 tagged J .it : return False;
202 tagged JR .it : return f.find(it.rsrc);
203 tagged JALR .it : return f.find(it.rsrc);
204 tagged JAL .it : return False;
205
206 // -- Cop0 ------------------------------------------------------
207
208 tagged MTC0 .it : return f.find(it.rsrc);
209 tagged MFC0 .it : return False;
210
211 // -- Illegal ---------------------------------------------------
212
213 default : return False;
214
215 endcase
216 endfunction
217 //-----------------------------------------------------------
218 // Reference processor
219 //-----------------------------------------------------------
220
221
222 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
223 //(* synthesize *)
224
225 module [CONNECTED_MODULE] mkProc( Proc );
226
227 //-----------------------------------------------------------
228 // Debug port
229
230 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
231
232
233 //-----------------------------------------------------------
234 // State
235
236 // Standard processor state
237
238 Reg#(Addr) pc <- mkReg(32'h00001000);
239 Reg#(Epoch) epoch <- mkReg(0);
240 Reg#(Stage) stage <- mkReg(PCgen);
241 BRFile rf <- mkBRFile;
242
243 // Branch Prediction
244 BranchPred bp <- mkBranchPred();
245 FIFO#(PCStat) execpc <- mkLFIFO();
246
247 // Pipelines
248 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
249 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
250
251 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
252 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
253 Reg#(Bool) cp0_statsEn <- mkReg(False);
254
255 // Memory request/response state
256
257 FIFO#(InstReq) instReqQ <- mkBFIFO1();
258 FIFO#(InstResp) instRespQ <- mkFIFO();
259
260 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
261 FIFO#(DataResp) dataRespQ <- mkFIFO();
262
263 // Audio I/O
264 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
265 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
266
267
268 // Statistics state (2010)
269 // Reg#(Stat) num_cycles <- mkReg(0);
270 // Reg#(Stat) num_inst <- mkReg(0);
271
272 //Or:
273 // Statistics state
274 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
275 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
276
277 //-----------------------------------------------------------
278 // Rules
279
280 (* descending_urgency = "exec, pcgen" *)
281 rule pcgen; //( stage == PCgen );
282 let pc_plus4 = pc + 4;
283
284 traceTiny("mkProc", "pc",pc);
285 traceTiny("mkProc", "pcgen","P");
286 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
287
288 let next_pc = bp.get(pc);
289 if (next_pc matches tagged Valid .npc)
290 begin
291 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
292 pc <= npc;
293 end
294 else
295 begin
296 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
297 pc <= pc_plus4;
298 end
299
300 endrule
301
302 rule discard (instRespQ.first() matches tagged LoadResp .ld
303 &&& ld.tag != epoch);
304 traceTiny("mkProc", "stage", "D");
305 instRespQ.deq();
306 endrule
307
308 (* conflict_free = "exec, writeback" *)
309 rule exec (instRespQ.first() matches tagged LoadResp.ld
310 &&& (ld.tag == epoch)
311 &&& unpack(ld.data) matches .inst
312 &&& !stall(inst, wbQ));
313
314 // Some abbreviations
315 let sext = signExtend;
316 let zext = zeroExtend;
317 let sra = signedShiftRight;
318
319 // Get the instruction
320
321 instRespQ.deq();
322 Instr inst
323 = case ( instRespQ.first() ) matches
324 tagged LoadResp .ld : return unpack(ld.data);
325 tagged StoreResp .st : return ?;
326 endcase;
327
328 // Get the PC info
329 let instrpc = pcQ.first().qpc;
330 let pc_plus4 = instrpc + 4;
331
332 Bool branchTaken = False;
333 Addr newPC = pc_plus4;
334
335 // Tracing
336 traceTiny("mkProc", "exec","X");
337 traceTiny("mkProc", "exInstTiny",inst);
338 traceFull("mkProc", "exInstFull",inst);
339
340 case ( inst ) matches
341
342 // -- Memory Ops ------------------------------------------------
343
344 tagged LW .it :
345 begin
346 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
347 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
348 wbQ.enq(tagged WB_Load it.rdst);
349 end
350
351 tagged SW .it :
352 begin
353 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
354 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
355 wbQ.enq(tagged WB_Store);
356 end
357
358 // -- Simple Ops ------------------------------------------------
359
360 tagged ADDIU .it :
361 begin
362 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
363 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
364 end
365 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
366 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
367 tagged ANDI .it :
368 begin
369 Bit#(32) zext_it_imm = zext(it.imm);
370 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
371 end
372 tagged ORI .it :
373 begin
374 Bit#(32) zext_it_imm = zext(it.imm);
375 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
376 end
377 tagged XORI .it :
378 begin
379 Bit#(32) zext_it_imm = zext(it.imm);
380 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
381 end
382 tagged LUI .it :
383 begin
384 Bit#(32) zext_it_imm = zext(it.imm);
385 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
386 end
387
388 tagged SLL .it :
389 begin
390 Bit#(32) zext_it_shamt = zext(it.shamt);
391 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
392 end
393 tagged SRL .it :
394 begin
395 Bit#(32) zext_it_shamt = zext(it.shamt);
396 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
397 end
398 tagged SRA .it :
399 begin
400 Bit#(32) zext_it_shamt = zext(it.shamt);
401 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
402 end
403 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
404 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
405 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
406 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
407 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
408 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
409 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
410 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
411 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
412 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
413 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
414
415 // -- Branches --------------------------------------------------
416
417 tagged BLEZ .it :
418 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
419 begin
420 newPC = pc_plus4 + (sext(it.offset) << 2);
421 branchTaken = True;
422 end
423
424 tagged BGTZ .it :
425 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
426 begin
427 newPC = pc_plus4 + (sext(it.offset) << 2);
428 branchTaken = True;
429 end
430
431 tagged BLTZ .it :
432 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
433 begin
434 newPC = pc_plus4 + (sext(it.offset) << 2);
435 branchTaken = True;
436 end
437
438 tagged BGEZ .it :
439 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
440 begin
441 newPC = pc_plus4 + (sext(it.offset) << 2);
442 branchTaken = True;
443 end
444
445 tagged BEQ .it :
446 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
447 begin
448 newPC = pc_plus4 + (sext(it.offset) << 2);
449 branchTaken = True;
450 end
451
452 tagged BNE .it :
453 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
454 begin
455 newPC = pc_plus4 + (sext(it.offset) << 2);
456 branchTaken = True;
457 end
458
459 // -- Jumps -----------------------------------------------------
460
461 tagged J .it :
462 begin
463 newPC = { pc_plus4[31:28], it.target, 2'b0 };
464 branchTaken = True;
465 end
466
467 tagged JR .it :
468 begin
469 newPC = rf.rd1(it.rsrc);
470 branchTaken = True;
471 end
472
473 tagged JAL .it :
474 begin
475 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
476 newPC = { pc_plus4[31:28], it.target, 2'b0 };
477 branchTaken = True;
478 end
479
480 tagged JALR .it :
481 begin
482 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
483 newPC = rf.rd1(it.rsrc);
484 branchTaken = True;
485 end
486
487 // -- Cop0 ------------------------------------------------------
488
489 tagged MTC0 .it :
490 begin
491 case ( it.cop0dst )
492 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
493 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
494 default :
495 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
496 endcase
497 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
498 end
499
500 //this is host stuff?
501 tagged MFC0 .it :
502 begin
503 case ( it.cop0src )
504 // not actually an ALU instruction but don't have the format otherwise
505 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
506 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
507 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
508 default :
509 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
510 endcase
511 end
512
513 // -- Illegal ---------------------------------------------------
514
515 default :
516 $display( " RTL-ERROR : %m : Illegal instruction !" );
517
518 endcase
519
520 //evaluate branch prediction
521 Addr ppc = pcQ.first().qnxtpc; //predicted branch
522 if (ppc != newPC) //prediction wrong
523 begin
524 epoch <= pcQ.first().qepoch + 1;
525 bp.upd(instrpc, newPC); //update branch predictor
526 pcQ.clear();
527 pc <= newPC;
528 end
529 else
530 pcQ.deq();
531
532 if ( cp0_statsEn )
533 num_inst.incr();
534
535 endrule
536
537 rule writeback; // ( stage == Writeback );
538 traceTiny("mkProc", "writeback","W");
539
540
541 // get what to do off the writeback queue
542 wbQ.deq();
543 case (wbQ.first()) matches
544 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
545 tagged WB_Load .regWr :
546 begin
547 dataRespQ.deq();
548 if (dataRespQ.first() matches tagged LoadResp .ld)
549 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
550 end
551 tagged WB_Store : dataRespQ.deq();
552 tagged WB_Host .dat : noAction;
553 endcase
554
555 endrule
556
557 rule inc_num_cycles;
558 if ( cp0_statsEn )
559 num_cycles.incr();
560 endrule
561
562 (* conservative_implicit_conditions *)
563 rule handleCPUToHost;
564 let req <- server_stub.acceptRequest_ReadCPUToHost();
565 case (req)
566 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
567 1: server_stub.sendResponse_ReadCPUToHost(pc);
568 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
569 endcase
570 endrule
571
572 // for now, we don't do anything.
573 rule connectAudioReqResp;
574 // $display("rlm: PROCESSOR copies a datum\n");
575 outAudioFifo.enq(inAudioFifo.first());
576 inAudioFifo.deq;
577 endrule
578
579 // Server items & rules:
580
581 rule feedInput;
582 let command <- server_stub.acceptRequest_SendUnprocessedStream();
583 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
584 if(ctrl == EndOfFile)
585 begin
586 // $display("lsp: PROCESSOR received EOF ");
587 inAudioFifo.enq(tagged EndOfFile);
588 end
589 else
590 begin
591 // $display("lsp: PROCESSOR received Data ");
592 inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
593 end
594 endrule
595
596
597 //-----------------------------------------------------------
598 // Methods
599
600 interface Client imem_client;
601 interface Get request = fifoToGet(instReqQ);
602 interface Put response = fifoToPut(instRespQ);
603 endinterface
604
605 interface Client dmem_client;
606 interface Get request = fifoToGet(dataReqQ);
607 interface Put response = fifoToPut(dataRespQ);
608 endinterface
609
610 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
611
612 // interface CPUToHost tohost;
613 // method Bit#(32) cpuToHost(int req);
614 // return (case (req)
615 // 0: cp0_tohost;
616 // 1: pc;
617 // 2: zeroExtend(pack(stage));
618 // endcase);
619 // endmethod
620 // endinterface
621
622 interface Get sampleOutput = fifoToGet(outAudioFifo);
623
624 endmodule
625