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annotate modules/bluespec/Pygar/core/#Processor.bsv# @ 26:f5dfbe28fa59 pygar svn.27

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[svn r27] Fixed Instruction trace issue.
author punk
date Fri, 30 Apr 2010 09:03:10 -0400
parents
children 99519a031813
rev   line source
punk@26 1 /// The MIT License
punk@26 2
punk@26 3 // Copyright (c) 2009 Massachusetts Institute of Technology
punk@26 4
punk@26 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@26 6 // of this software and associated documentation files (the "Software"), to deal
punk@26 7 // in the Software without restriction, including without limitation the rights
punk@26 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@26 9 // copies of the Software, and to permit persons to whom the Software is
punk@26 10 // furnished to do so, subject to the following conditions:
punk@26 11
punk@26 12 // The above copyright notice and this permission notice shall be included in
punk@26 13 // all copies or substantial portions of the Software.
punk@26 14
punk@26 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@26 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@26 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@26 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@26 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@26 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@26 21 // THE SOFTWARE.
punk@26 22
punk@26 23
punk@26 24 import Connectable::*;
punk@26 25 import GetPut::*;
punk@26 26 import ClientServer::*;
punk@26 27 import RegFile::*;
punk@26 28
punk@26 29 import FIFO::*;
punk@26 30 import FIFOF::*;
punk@26 31 import SFIFO::*;
punk@26 32 import RWire::*;
punk@26 33 import Trace::*;
punk@26 34 import BFIFO::*;
punk@26 35 import ProcTypes::*;
punk@26 36 import BRegFile::*;
punk@26 37 import BranchPred::*;
punk@26 38 //import PathTypes::*; This is only there to force the debugging
punk@26 39
punk@26 40 //AWB includes
punk@26 41 `include "asim/provides/low_level_platform_interface.bsh"
punk@26 42 `include "asim/provides/soft_connections.bsh"
punk@26 43 `include "asim/provides/common_services.bsh"
punk@26 44
punk@26 45 // Local includes
punk@26 46 //`include "asim/provides/processor_library.bsh" (included above directly)
punk@26 47 `include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
punk@26 48 `include "asim/provides/common_services.bsh"
punk@26 49 `include "asim/dict/STATS_PROCESSOR.bsh"
punk@26 50 `include "asim/provides/processor_library.bsh"
punk@26 51
punk@26 52 // Local includes. Look for the correspondingly named .awb files
punk@26 53 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@26 54 // to find the actual Bluespec files which are used to generate
punk@26 55 // these includes. These files are specific to this audio processing
punk@26 56 // pipeline
punk@26 57
punk@26 58 `include "asim/provides/audio_pipe_types.bsh"
punk@26 59
punk@26 60 //interface CPUToHost;
punk@26 61 // method Bit#(32) cpuToHost(int req);
punk@26 62 //endinterface
punk@26 63
punk@26 64 interface Proc;
punk@26 65
punk@26 66 // Interface from processor to caches
punk@26 67 interface Client#(DataReq,DataResp) dmem_client;
punk@26 68 interface Client#(InstReq,InstResp) imem_client;
punk@26 69
punk@26 70 // Interface for enabling/disabling statistics on the rest of the core
punk@26 71 interface Get#(Bool) statsEn_get;
punk@26 72
punk@26 73 // // Interface to host
punk@26 74 // interface CPUToHost tohost;
punk@26 75
punk@26 76 // Interface to Audio Pipeline
punk@26 77 interface Get#(AudioProcessorUnit) sampleOutput;
punk@26 78
punk@26 79 endinterface
punk@26 80
punk@26 81 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
punk@26 82 //interface AudioOut;
punk@26 83 // interface Get#(AudioProcessorUnit) audioSampleOutput;
punk@26 84 //endinterface
punk@26 85
punk@26 86 //interface AudioIn;
punk@26 87 // interface Put#(AudioProcessorUnit) audioSampleInput;
punk@26 88 //endinterface
punk@26 89
punk@26 90 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
punk@26 91
punk@26 92 //-----------------------------------------------------------
punk@26 93 // Register file module
punk@26 94 //-----------------------------------------------------------
punk@26 95
punk@26 96 interface BRFile;
punk@26 97 method Action wr( Rindx rindx, Bit#(32) data );
punk@26 98 method Bit#(32) rd1( Rindx rindx );
punk@26 99 method Bit#(32) rd2( Rindx rindx );
punk@26 100 endinterface
punk@26 101
punk@26 102 module mkBRFile( BRFile );
punk@26 103
punk@26 104 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
punk@26 105
punk@26 106 method Action wr( Rindx rindx, Bit#(32) data );
punk@26 107 rfile.upd( rindx, data );
punk@26 108 endmethod
punk@26 109
punk@26 110 method Bit#(32) rd1( Rindx rindx );
punk@26 111 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
punk@26 112 endmethod
punk@26 113
punk@26 114 method Bit#(32) rd2( Rindx rindx );
punk@26 115 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
punk@26 116 endmethod
punk@26 117
punk@26 118 endmodule
punk@26 119
punk@26 120 //-----------------------------------------------------------
punk@26 121 // Helper functions
punk@26 122 //-----------------------------------------------------------
punk@26 123
punk@26 124 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
punk@26 125 return zeroExtend( pack( signedLT(val1,val2) ) );
punk@26 126 endfunction
punk@26 127
punk@26 128 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
punk@26 129 return zeroExtend( pack( val1 < val2 ) );
punk@26 130 endfunction
punk@26 131
punk@26 132 function Bit#(32) rshft( Bit#(32) val );
punk@26 133 return zeroExtend(val[4:0]);
punk@26 134 endfunction
punk@26 135
punk@26 136
punk@26 137 //-----------------------------------------------------------
punk@26 138 // Find funct for wbQ
punk@26 139 //-----------------------------------------------------------
punk@26 140 function Bool findwbf(Rindx fVal, WBResult cmpVal);
punk@26 141 case (cmpVal) matches
punk@26 142 tagged WB_ALU {data:.res, dest:.rd} :
punk@26 143 return (fVal == rd);
punk@26 144 tagged WB_Load .rd :
punk@26 145 return (fVal == rd);
punk@26 146 tagged WB_Store .st :
punk@26 147 return False;
punk@26 148 tagged WB_Host .x :
punk@26 149 return False;
punk@26 150 endcase
punk@26 151 endfunction
punk@26 152
punk@26 153
punk@26 154 //-----------------------------------------------------------
punk@26 155 // Stall funct for wbQ
punk@26 156 //-----------------------------------------------------------
punk@26 157 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
punk@26 158 case (inst) matches
punk@26 159 // -- Memory Ops ------------------------------------------------
punk@26 160 tagged LW .it :
punk@26 161 return f.find(it.rbase);
punk@26 162 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
punk@26 163 return (f.find(addr) || f.find2(dreg));
punk@26 164
punk@26 165 // -- Simple Ops ------------------------------------------------
punk@26 166 tagged ADDIU .it : return f.find(it.rsrc);
punk@26 167 tagged SLTI .it : return f.find(it.rsrc);
punk@26 168 tagged SLTIU .it : return f.find(it.rsrc);
punk@26 169 tagged ANDI .it : return f.find(it.rsrc);
punk@26 170 tagged ORI .it : return f.find(it.rsrc);
punk@26 171 tagged XORI .it : return f.find(it.rsrc);
punk@26 172
punk@26 173 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
punk@26 174 tagged SLL .it : return f.find(it.rsrc);
punk@26 175 tagged SRL .it : return f.find(it.rsrc);
punk@26 176 tagged SRA .it : return f.find(it.rsrc);
punk@26 177 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
punk@26 178 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
punk@26 179 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
punk@26 180 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 181 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 182 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 183 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 184 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 185 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 186 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 187 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 188
punk@26 189
punk@26 190 // -- Branches --------------------------------------------------
punk@26 191
punk@26 192 tagged BLEZ .it : return (f.find(it.rsrc));
punk@26 193 tagged BGTZ .it : return (f.find(it.rsrc));
punk@26 194 tagged BLTZ .it : return (f.find(it.rsrc));
punk@26 195 tagged BGEZ .it : return (f.find(it.rsrc));
punk@26 196 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 197 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 198
punk@26 199 // -- Jumps -----------------------------------------------------
punk@26 200
punk@26 201 tagged J .it : return False;
punk@26 202 tagged JR .it : return f.find(it.rsrc);
punk@26 203 tagged JALR .it : return f.find(it.rsrc);
punk@26 204 tagged JAL .it : return False;
punk@26 205
punk@26 206 // -- Cop0 ------------------------------------------------------
punk@26 207
punk@26 208 tagged MTC0 .it : return f.find(it.rsrc);
punk@26 209 tagged MFC0 .it : return False;
punk@26 210
punk@26 211 // -- Illegal ---------------------------------------------------
punk@26 212
punk@26 213 default : return False;
punk@26 214
punk@26 215 endcase
punk@26 216 endfunction
punk@26 217 //-----------------------------------------------------------
punk@26 218 // Reference processor
punk@26 219 //-----------------------------------------------------------
punk@26 220
punk@26 221
punk@26 222 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
punk@26 223 //(* synthesize *)
punk@26 224
punk@26 225 module [CONNECTED_MODULE] mkProc( Proc );
punk@26 226
punk@26 227 //-----------------------------------------------------------
punk@26 228 // Debug port
punk@26 229
punk@26 230 ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR();
punk@26 231
punk@26 232
punk@26 233 //-----------------------------------------------------------
punk@26 234 // State
punk@26 235
punk@26 236 // Standard processor state
punk@26 237
punk@26 238 Reg#(Addr) pc <- mkReg(32'h00001000);
punk@26 239 Reg#(Epoch) epoch <- mkReg(0);
punk@26 240 Reg#(Stage) stage <- mkReg(PCgen);
punk@26 241 BRFile rf <- mkBRFile;
punk@26 242
punk@26 243 // Branch Prediction
punk@26 244 BranchPred bp <- mkBranchPred();
punk@26 245 FIFO#(PCStat) execpc <- mkLFIFO();
punk@26 246
punk@26 247 // Pipelines
punk@26 248 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
punk@26 249 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
punk@26 250
punk@26 251 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
punk@26 252 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
punk@26 253 Reg#(Bool) cp0_statsEn <- mkReg(False);
punk@26 254
punk@26 255 // Memory request/response state
punk@26 256
punk@26 257 FIFO#(InstReq) instReqQ <- mkBFIFO1();
punk@26 258 FIFO#(InstResp) instRespQ <- mkFIFO();
punk@26 259
punk@26 260 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
punk@26 261 FIFO#(DataResp) dataRespQ <- mkFIFO();
punk@26 262
punk@26 263 // Audio I/O
punk@26 264 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
punk@26 265 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
punk@26 266
punk@26 267
punk@26 268 // Statistics state (2010)
punk@26 269 // Reg#(Stat) num_cycles <- mkReg(0);
punk@26 270 // Reg#(Stat) num_inst <- mkReg(0);
punk@26 271
punk@26 272 //Or:
punk@26 273 // Statistics state
punk@26 274 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
punk@26 275 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
punk@26 276
punk@26 277 //-----------------------------------------------------------
punk@26 278 // Rules
punk@26 279
punk@26 280 (* descending_urgency = "exec, pcgen" *)
punk@26 281 rule pcgen; //( stage == PCgen );
punk@26 282 let pc_plus4 = pc + 4;
punk@26 283
punk@26 284 traceTiny("mkProc", "pc",pc);
punk@26 285 traceTiny("mkProc", "pcgen","P");
punk@26 286 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
punk@26 287
punk@26 288 let next_pc = bp.get(pc);
punk@26 289 if (next_pc matches tagged Valid .npc)
punk@26 290 begin
punk@26 291 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
punk@26 292 pc <= npc;
punk@26 293 end
punk@26 294 else
punk@26 295 begin
punk@26 296 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
punk@26 297 pc <= pc_plus4;
punk@26 298 end
punk@26 299
punk@26 300 endrule
punk@26 301
punk@26 302 rule discard (instRespQ.first() matches tagged LoadResp .ld
punk@26 303 &&& ld.tag != epoch);
punk@26 304 traceTiny("mkProc", "stage", "D");
punk@26 305 instRespQ.deq();
punk@26 306 endrule
punk@26 307
punk@26 308 (* conflict_free = "exec, writeback" *)
punk@26 309 rule exec (instRespQ.first() matches tagged LoadResp.ld
punk@26 310 &&& (ld.tag == epoch)
punk@26 311 &&& unpack(ld.data) matches .inst
punk@26 312 &&& !stall(inst, wbQ));
punk@26 313
punk@26 314 // Some abbreviations
punk@26 315 let sext = signExtend;
punk@26 316 let zext = zeroExtend;
punk@26 317 let sra = signedShiftRight;
punk@26 318
punk@26 319 // Get the instruction
punk@26 320
punk@26 321 instRespQ.deq();
punk@26 322 Instr inst
punk@26 323 = case ( instRespQ.first() ) matches
punk@26 324 tagged LoadResp .ld : return unpack(ld.data);
punk@26 325 tagged StoreResp .st : return ?;
punk@26 326 endcase;
punk@26 327
punk@26 328 // Get the PC info
punk@26 329 let instrpc = pcQ.first().qpc;
punk@26 330 let pc_plus4 = instrpc + 4;
punk@26 331
punk@26 332 Bool branchTaken = False;
punk@26 333 Addr newPC = pc_plus4;
punk@26 334
punk@26 335 // Tracing
punk@26 336 traceTiny("mkProc", "exec","X");
punk@26 337 traceTiny("mkProc", "exInstTiny",inst);
punk@26 338 traceFull("mkProc", "exInstFull",inst);
punk@26 339
punk@26 340 case ( inst ) matches
punk@26 341
punk@26 342 // -- Memory Ops ------------------------------------------------
punk@26 343
punk@26 344 tagged LW .it :
punk@26 345 begin
punk@26 346 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
punk@26 347 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
punk@26 348 wbQ.enq(tagged WB_Load it.rdst);
punk@26 349 end
punk@26 350
punk@26 351 tagged SW .it :
punk@26 352 begin
punk@26 353 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
punk@26 354 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
punk@26 355 wbQ.enq(tagged WB_Store);
punk@26 356 end
punk@26 357
punk@26 358 // -- Simple Ops ------------------------------------------------
punk@26 359
punk@26 360 tagged ADDIU .it :
punk@26 361 begin
punk@26 362 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
punk@26 363 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
punk@26 364 end
punk@26 365 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
punk@26 366 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
punk@26 367 tagged ANDI .it :
punk@26 368 begin
punk@26 369 Bit#(32) zext_it_imm = zext(it.imm);
punk@26 370 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
punk@26 371 end
punk@26 372 tagged ORI .it :
punk@26 373 begin
punk@26 374 Bit#(32) zext_it_imm = zext(it.imm);
punk@26 375 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
punk@26 376 end
punk@26 377 tagged XORI .it :
punk@26 378 begin
punk@26 379 Bit#(32) zext_it_imm = zext(it.imm);
punk@26 380 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
punk@26 381 end
punk@26 382 tagged LUI .it :
punk@26 383 begin
punk@26 384 Bit#(32) zext_it_imm = zext(it.imm);
punk@26 385 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
punk@26 386 end
punk@26 387
punk@26 388 tagged SLL .it :
punk@26 389 begin
punk@26 390 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@26 391 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
punk@26 392 end
punk@26 393 tagged SRL .it :
punk@26 394 begin
punk@26 395 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@26 396 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
punk@26 397 end
punk@26 398 tagged SRA .it :
punk@26 399 begin
punk@26 400 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@26 401 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
punk@26 402 end
punk@26 403 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
punk@26 404 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
punk@26 405 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
punk@26 406 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
punk@26 407 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
punk@26 408 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
punk@26 409 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
punk@26 410 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
punk@26 411 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
punk@26 412 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
punk@26 413 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
punk@26 414
punk@26 415 // -- Branches --------------------------------------------------
punk@26 416
punk@26 417 tagged BLEZ .it :
punk@26 418 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
punk@26 419 begin
punk@26 420 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 421 branchTaken = True;
punk@26 422 end
punk@26 423
punk@26 424 tagged BGTZ .it :
punk@26 425 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
punk@26 426 begin
punk@26 427 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 428 branchTaken = True;
punk@26 429 end
punk@26 430
punk@26 431 tagged BLTZ .it :
punk@26 432 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
punk@26 433 begin
punk@26 434 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 435 branchTaken = True;
punk@26 436 end
punk@26 437
punk@26 438 tagged BGEZ .it :
punk@26 439 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
punk@26 440 begin
punk@26 441 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 442 branchTaken = True;
punk@26 443 end
punk@26 444
punk@26 445 tagged BEQ .it :
punk@26 446 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
punk@26 447 begin
punk@26 448 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 449 branchTaken = True;
punk@26 450 end
punk@26 451
punk@26 452 tagged BNE .it :
punk@26 453 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
punk@26 454 begin
punk@26 455 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 456 branchTaken = True;
punk@26 457 end
punk@26 458
punk@26 459 // -- Jumps -----------------------------------------------------
punk@26 460
punk@26 461 tagged J .it :
punk@26 462 begin
punk@26 463 newPC = { pc_plus4[31:28], it.target, 2'b0 };
punk@26 464 branchTaken = True;
punk@26 465 end
punk@26 466
punk@26 467 tagged JR .it :
punk@26 468 begin
punk@26 469 newPC = rf.rd1(it.rsrc);
punk@26 470 branchTaken = True;
punk@26 471 end
punk@26 472
punk@26 473 tagged JAL .it :
punk@26 474 begin
punk@26 475 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
punk@26 476 newPC = { pc_plus4[31:28], it.target, 2'b0 };
punk@26 477 branchTaken = True;
punk@26 478 end
punk@26 479
punk@26 480 tagged JALR .it :
punk@26 481 begin
punk@26 482 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
punk@26 483 newPC = rf.rd1(it.rsrc);
punk@26 484 branchTaken = True;
punk@26 485 end
punk@26 486
punk@26 487 // -- Cop0 ------------------------------------------------------
punk@26 488
punk@26 489 tagged MTC0 .it :
punk@26 490 begin
punk@26 491 case ( it.cop0dst )
punk@26 492 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
punk@26 493 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
punk@26 494 default :
punk@26 495 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
punk@26 496 endcase
punk@26 497 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
punk@26 498 end
punk@26 499
punk@26 500 //this is host stuff?
punk@26 501 tagged MFC0 .it :
punk@26 502 begin
punk@26 503 case ( it.cop0src )
punk@26 504 // not actually an ALU instruction but don't have the format otherwise
punk@26 505 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
punk@26 506 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
punk@26 507 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
punk@26 508 default :
punk@26 509 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
punk@26 510 endcase
punk@26 511 end
punk@26 512
punk@26 513 // -- Illegal ---------------------------------------------------
punk@26 514
punk@26 515 default :
punk@26 516 $display( " RTL-ERROR : %m : Illegal instruction !" );
punk@26 517
punk@26 518 endcase
punk@26 519
punk@26 520 //evaluate branch prediction
punk@26 521 Addr ppc = pcQ.first().qnxtpc; //predicted branch
punk@26 522 if (ppc != newPC) //prediction wrong
punk@26 523 begin
punk@26 524 epoch <= pcQ.first().qepoch + 1;
punk@26 525 bp.upd(instrpc, newPC); //update branch predictor
punk@26 526 pcQ.clear();
punk@26 527 pc <= newPC;
punk@26 528 end
punk@26 529 else
punk@26 530 pcQ.deq();
punk@26 531
punk@26 532 if ( cp0_statsEn )
punk@26 533 num_inst.incr();
punk@26 534
punk@26 535 endrule
punk@26 536
punk@26 537 rule writeback; // ( stage == Writeback );
punk@26 538 traceTiny("mkProc", "writeback","W");
punk@26 539
punk@26 540
punk@26 541 // get what to do off the writeback queue
punk@26 542 wbQ.deq();
punk@26 543 case (wbQ.first()) matches
punk@26 544 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
punk@26 545 tagged WB_Load .regWr :
punk@26 546 begin
punk@26 547 dataRespQ.deq();
punk@26 548 if (dataRespQ.first() matches tagged LoadResp .ld)
punk@26 549 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
punk@26 550 end
punk@26 551 tagged WB_Store : dataRespQ.deq();
punk@26 552 tagged WB_Host .dat : noAction;
punk@26 553 endcase
punk@26 554
punk@26 555 endrule
punk@26 556
punk@26 557 rule inc_num_cycles;
punk@26 558 if ( cp0_statsEn )
punk@26 559 num_cycles.incr();
punk@26 560 endrule
punk@26 561
punk@26 562 (* conservative_implicit_conditions *)
punk@26 563 rule handleCPUToHost;
punk@26 564 let req <- server_stub.acceptRequest_ReadCPUToHost();
punk@26 565 case (req)
punk@26 566 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
punk@26 567 1: server_stub.sendResponse_ReadCPUToHost(pc);
punk@26 568 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
punk@26 569 endcase
punk@26 570 endrule
punk@26 571
punk@26 572 // for now, we don't do anything.
punk@26 573 rule connectAudioReqResp;
punk@26 574 // $display("rlm: PROCESSOR copies a datum\n");
punk@26 575 outAudioFifo.enq(inAudioFifo.first());
punk@26 576 inAudioFifo.deq;
punk@26 577 endrule
punk@26 578
punk@26 579 // Server items & rules:
punk@26 580
punk@26 581 rule feedInput;
punk@26 582 let command <- server_stub.acceptRequest_SendUnprocessedStream();
punk@26 583 AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
punk@26 584 if(ctrl == EndOfFile)
punk@26 585 begin
punk@26 586 // $display("lsp: PROCESSOR received EOF ");
punk@26 587 inAudioFifo.enq(tagged EndOfFile);
punk@26 588 end
punk@26 589 else
punk@26 590 begin
punk@26 591 // $display("lsp: PROCESSOR received Data ");
punk@26 592 inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
punk@26 593 end
punk@26 594 endrule
punk@26 595
punk@26 596
punk@26 597 //-----------------------------------------------------------
punk@26 598 // Methods
punk@26 599
punk@26 600 interface Client imem_client;
punk@26 601 interface Get request = fifoToGet(instReqQ);
punk@26 602 interface Put response = fifoToPut(instRespQ);
punk@26 603 endinterface
punk@26 604
punk@26 605 interface Client dmem_client;
punk@26 606 interface Get request = fifoToGet(dataReqQ);
punk@26 607 interface Put response = fifoToPut(dataRespQ);
punk@26 608 endinterface
punk@26 609
punk@26 610 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
punk@26 611
punk@26 612 // interface CPUToHost tohost;
punk@26 613 // method Bit#(32) cpuToHost(int req);
punk@26 614 // return (case (req)
punk@26 615 // 0: cp0_tohost;
punk@26 616 // 1: pc;
punk@26 617 // 2: zeroExtend(pack(stage));
punk@26 618 // endcase);
punk@26 619 // endmethod
punk@26 620 // endinterface
punk@26 621
punk@26 622 interface Get sampleOutput = fifoToGet(outAudioFifo);
punk@26 623
punk@26 624 endmodule
punk@26 625