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comparison modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv @ 51:9fe5ed4af92d pygar svn.52

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[svn r52] tested having multiple cores
author punk
date Wed, 05 May 2010 17:01:04 -0400
parents 61f6267cb3db
children 6179c07c21d7
comparison
equal deleted inserted replaced
50:2b18894f75e2 51:9fe5ed4af92d
33 `include "asim/provides/low_level_platform_interface.bsh" 33 `include "asim/provides/low_level_platform_interface.bsh"
34 `include "asim/provides/soft_connections.bsh" 34 `include "asim/provides/soft_connections.bsh"
35 `include "asim/provides/processor_library.bsh" 35 `include "asim/provides/processor_library.bsh"
36 `include "asim/provides/fpga_components.bsh" 36 `include "asim/provides/fpga_components.bsh"
37 `include "asim/provides/common_services.bsh" 37 `include "asim/provides/common_services.bsh"
38 `include "asim/dict/STATS_INST_CACHE.bsh"
39 38
40 interface ICache#( type req_t, type resp_t ); 39 interface ICache#( type req_t, type resp_t );
41 40
42 // Interface from processor to cache 41 // Interface from processor to cache
43 interface Server#(req_t,resp_t) proc_server; 42 interface Server#(req_t,resp_t) proc_server;