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comparison core/src/MemArb.bsv @ 1:91a1f76ddd62 pygar svn.2

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[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
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0:6d1ff93e3afa 1:91a1f76ddd62
1 // The MIT License
2
3 // Copyright (c) 2009 Massachusetts Institute of Technology
4
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
11
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
14
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
22
23 import Connectable::*;
24 import GetPut::*;
25 import ClientServer::*;
26 import FIFOF::*;
27 import FIFO::*;
28
29 import BFIFO::*;
30 import MemTypes::*;
31 import Trace::*;
32
33 interface MemArb;
34
35 interface Server#(MainMemReq,MainMemResp) cache0_server;
36 interface Server#(MainMemReq,MainMemResp) cache1_server;
37 interface Client#(MainMemReq,MainMemResp) mmem_client;
38
39 endinterface
40
41 typedef enum { REQ0, REQ1 } ReqPtr deriving(Eq,Bits);
42
43 (* synthesize *)
44 module mkMemArb( MemArb );
45
46 //-----------------------------------------------------------
47 // State
48
49 FIFOF#(MainMemReq) req0Q <- mkFIFOF1();
50 FIFO#(MainMemResp) resp0Q <- mkFIFO1();
51
52 FIFOF#(MainMemReq) req1Q <- mkFIFOF1();
53 FIFO#(MainMemResp) resp1Q <- mkFIFO1();
54
55 FIFO#(MainMemReq) mreqQ <- mkFIFO1();
56 FIFO#(MainMemResp) mrespQ <- mkFIFO1();
57
58 Reg#(ReqPtr) nextReq <- mkReg(REQ0);
59
60 //-----------------------------------------------------------
61 // Some wires
62
63 let req0avail = req0Q.notEmpty();
64 let req1avail = req1Q.notEmpty();
65
66 //-----------------------------------------------------------
67 // Rules
68
69 rule chooseReq0 ( req0avail && (!req1avail || (nextReq == REQ0)) );
70 traceTiny("mkMemArb", "memArb req0",req0Q.first());
71
72 // Rewrite tag field if this is a load ...
73 MainMemReq mreq
74 = case ( req0Q.first() ) matches
75 tagged LoadReq .ld : return LoadReq { tag:0, addr:ld.addr };
76 tagged StoreReq .st : return req0Q.first();
77 endcase;
78
79 // Send out the request
80 mreqQ.enq(mreq);
81 nextReq <= REQ1;
82 req0Q.deq();
83
84 endrule
85
86 rule chooseReq1 ( req1avail && (!req0avail || (nextReq == REQ1)) );
87 traceTiny("mkMemArb", "memArb req1",req1Q.first);
88
89 // Rewrite tag field if this is a load ...
90 MainMemReq mreq
91 = case ( req1Q.first() ) matches
92 tagged LoadReq .ld : return LoadReq { tag:1, addr:ld.addr };
93 tagged StoreReq .st : return req1Q.first();
94 endcase;
95
96 // Send out the request
97 mreqQ.enq(mreq);
98 nextReq <= REQ0;
99 req1Q.deq();
100
101 endrule
102
103 rule returnResp;
104 traceTiny("mkMemArb", "resp",mrespQ.first());
105
106 // Use tag to figure out where to send response
107 mrespQ.deq();
108 let tag
109 = case ( mrespQ.first() ) matches
110 tagged LoadResp .ld : return ld.tag;
111 tagged StoreResp .st : return st.tag;
112 endcase;
113
114 if ( tag == 0 )
115 resp0Q.enq(mrespQ.first());
116 else
117 resp1Q.enq(mrespQ.first());
118
119 endrule
120
121 //-----------------------------------------------------------
122 // Methods
123
124 interface Server cache0_server;
125 interface Put request = toPut(req0Q);
126 interface Get response = toGet(resp0Q);
127 endinterface
128
129 interface Server cache1_server;
130 interface Put request = toPut(req1Q);
131 interface Get response = toGet(resp1Q);
132 endinterface
133
134 interface Client mmem_client;
135 interface Get request = toGet(mreqQ);
136 interface Put response = toPut(mrespQ);
137 endinterface
138
139 endmodule
140
141