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comparison core/src/InstCacheBlocking.bsv @ 1:91a1f76ddd62 pygar svn.2

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[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
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0:6d1ff93e3afa 1:91a1f76ddd62
1 // The MIT License
2
3 // Copyright (c) 2009 Massachusetts Institute of Technology
4
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
11
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
14
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
22
23 import Connectable::*;
24 import GetPut::*;
25 import ClientServer::*;
26 import RegFile::*;
27 import FIFO::*;
28 import FIFOF::*;
29 import RWire::*;
30
31 import BFIFO::*;
32 import MemTypes::*;
33 import ProcTypes::*;
34 import Trace::*;
35
36 interface ICacheStats;
37 interface Get#(Stat) num_accesses;
38 interface Get#(Stat) num_misses;
39 interface Get#(Stat) num_evictions;
40 endinterface
41
42 interface ICache#( type req_t, type resp_t );
43
44 // Interface from processor to cache
45 interface Server#(req_t,resp_t) proc_server;
46
47 // Interface from cache to main memory
48 interface Client#(MainMemReq,MainMemResp) mmem_client;
49
50 // Interface for enabling/disabling statistics
51 interface Put#(Bool) statsEn_put;
52
53 // Interface for collecting statistics
54 interface ICacheStats stats;
55
56 endinterface
57
58 //----------------------------------------------------------------------
59 // Cache Types
60 //----------------------------------------------------------------------
61
62 typedef 10 CacheLineIndexSz;
63 typedef 20 CacheLineTagSz;
64 typedef 32 CacheLineSz;
65
66 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
67 typedef Bit#(CacheLineTagSz) CacheLineTag;
68 typedef Bit#(CacheLineSz) CacheLine;
69
70 typedef enum
71 {
72 Init,
73 Access,
74 Evict,
75 RefillReq,
76 RefillResp
77 }
78 CacheStage
79 deriving (Eq,Bits);
80
81 //----------------------------------------------------------------------
82 // Helper functions
83 //----------------------------------------------------------------------
84
85 function Bit#(AddrSz) getAddr( InstReq req );
86
87 Bit#(AddrSz) addr = ?;
88 case ( req ) matches
89 tagged LoadReq .ld : addr = ld.addr;
90 tagged StoreReq .st : addr = st.addr;
91 endcase
92
93 return addr;
94
95 endfunction
96
97 function CacheLineIndex getCacheLineIndex( InstReq req );
98 Bit#(AddrSz) addr = getAddr(req);
99 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
100 return index;
101 endfunction
102
103 function CacheLineTag getCacheLineTag( InstReq req );
104 Bit#(AddrSz) addr = getAddr(req);
105 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
106 return tag;
107 endfunction
108
109 function Bit#(AddrSz) getCacheLineAddr( InstReq req );
110 Bit#(AddrSz) addr = getAddr(req);
111 return ((addr >> 2) << 2);
112 endfunction
113
114 //----------------------------------------------------------------------
115 // Main module
116 //----------------------------------------------------------------------
117
118 (* doc = "synthesis attribute ram_style mkInstCache distributed;" *)
119 (* synthesize *)
120 module mkInstCache( ICache#(InstReq,InstResp) );
121
122 //-----------------------------------------------------------
123 // State
124
125 Reg#(CacheStage) stage <- mkReg(Init);
126
127 RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull();
128 RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull();
129
130 FIFO#(InstReq) reqQ <- mkFIFO();
131 FIFOF#(InstResp) respQ <- mkBFIFOF1();
132
133 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
134 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
135
136 Reg#(CacheLineIndex) initCounter <- mkReg(1);
137
138 // Statistics state
139
140 Reg#(Bool) statsEn <- mkReg(False);
141
142 Reg#(Stat) numAccesses <- mkReg(0);
143 Reg#(Stat) numMisses <- mkReg(0);
144 Reg#(Stat) numEvictions <- mkReg(0);
145
146 //-----------------------------------------------------------
147 // Name some wires
148
149 let req = reqQ.first();
150 let reqIndex = getCacheLineIndex(req);
151 let reqTag = getCacheLineTag(req);
152 let reqCacheLineAddr = getCacheLineAddr(req);
153 let refill = mainMemRespQ.first();
154
155 //-----------------------------------------------------------
156 // Initialize
157
158 rule init ( stage == Init );
159 traceTiny("mkInstCacheBlocking", "stage","i");
160 initCounter <= initCounter + 1;
161 cacheTagRam.upd(initCounter,Invalid);
162 if ( initCounter == 0 )
163 stage <= Access;
164 endrule
165
166 //-----------------------------------------------------------
167 // Cache access rule
168
169 rule access ( (stage == Access) && respQ.notFull() );
170
171 // Statistics
172
173 if ( statsEn )
174 numAccesses <= numAccesses + 1;
175
176 // Check tag and valid bit to see if this is a hit or a miss
177
178 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
179
180 // Handle cache hits ...
181
182 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
183 begin
184 traceTiny("mkInstCacheBlocking", "hitMiss","h");
185 reqQ.deq();
186
187 case ( req ) matches
188
189 tagged LoadReq .ld :
190 respQ.enq( LoadResp { tag : ld.tag, data : cacheDataRam.sub(reqIndex) } );
191
192 tagged StoreReq .st :
193 $display( " RTL-ERROR : %m : Stores are not allowed on the inst port!" );
194
195 endcase
196
197 end
198
199 // Handle cache misses - since lines in instruction cache are
200 // never dirty we can always immediately issue a refill request
201
202 else
203 begin
204 traceTiny("mkInstCacheBlocking", "hitMiss","m");
205 if ( statsEn )
206 numMisses <= numMisses + 1;
207 if ( statsEn )
208 if ( isJust(cacheLineTag) )
209 numEvictions <= numEvictions + 1;
210
211 MainMemReq rfReq
212 = LoadReq { tag : 0,
213 addr : reqCacheLineAddr };
214
215 mainMemReqQ.enq(rfReq);
216 stage <= RefillResp;
217 end
218
219 endrule
220
221 //-----------------------------------------------------------
222 // Refill response rule
223
224 rule refillResp ( stage == RefillResp );
225 traceTiny("mkInstCacheBlocking", "stage","R");
226 traceTiny("mkInstCacheBlocking", "refill",refill);
227
228 // Write the new data into the cache and update the tag
229
230 mainMemRespQ.deq();
231 case ( mainMemRespQ.first() ) matches
232
233 tagged LoadResp .ld :
234 begin
235 cacheTagRam.upd(reqIndex,Valid(reqTag));
236 cacheDataRam.upd(reqIndex,ld.data);
237 end
238
239 tagged StoreResp .st :
240 noAction;
241
242 endcase
243
244 stage <= Access;
245 endrule
246
247 //-----------------------------------------------------------
248 // Methods
249
250 interface Client mmem_client;
251 interface Get request = fifoToGet(mainMemReqQ);
252 interface Put response = fifoToPut(mainMemRespQ);
253 endinterface
254
255 interface Server proc_server;
256 interface Put request = tracePut("mkInstCacheBlocking", "reqTiny",toPut(reqQ));
257 interface Get response = traceGet("mkInstCacheBlocking", "respTiny",toGet(respQ));
258 endinterface
259
260 interface Put statsEn_put = toPut(asReg(statsEn));
261
262 interface ICacheStats stats;
263 interface Get num_accesses = toGet(asReg(numAccesses));
264 interface Get num_misses = toGet(asReg(numMisses));
265 interface Get num_evictions = toGet(asReg(numEvictions));
266 endinterface
267
268 endmodule
269