Mercurial > pygar
comparison core/src/DataCacheBlocking.bsv @ 1:91a1f76ddd62 pygar svn.2
[svn r2] Adding initial lab 5 source
author | punk |
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date | Tue, 13 Apr 2010 17:34:33 -0400 |
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1 // The MIT License | |
2 | |
3 // Copyright (c) 2009 Massachusetts Institute of Technology | |
4 | |
5 // Permission is hereby granted, free of charge, to any person obtaining a copy | |
6 // of this software and associated documentation files (the "Software"), to deal | |
7 // in the Software without restriction, including without limitation the rights | |
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
9 // copies of the Software, and to permit persons to whom the Software is | |
10 // furnished to do so, subject to the following conditions: | |
11 | |
12 // The above copyright notice and this permission notice shall be included in | |
13 // all copies or substantial portions of the Software. | |
14 | |
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | |
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
21 // THE SOFTWARE. | |
22 | |
23 import Connectable::*; | |
24 import GetPut::*; | |
25 import ClientServer::*; | |
26 import RegFile::*; | |
27 import FIFO::*; | |
28 import FIFOF::*; | |
29 | |
30 import BFIFO::*; | |
31 import MemTypes::*; | |
32 import ProcTypes::*; | |
33 import Trace::*; | |
34 | |
35 interface DCacheStats; | |
36 interface Get#(Stat) num_accesses; | |
37 interface Get#(Stat) num_misses; | |
38 interface Get#(Stat) num_writebacks; | |
39 endinterface | |
40 | |
41 interface DCache#( type req_t, type resp_t ); | |
42 | |
43 // Interface from processor to cache | |
44 interface Server#(req_t,resp_t) proc_server; | |
45 | |
46 // Interface from cache to main memory | |
47 interface Client#(MainMemReq,MainMemResp) mmem_client; | |
48 | |
49 // Interface for enabling/disabling statistics | |
50 interface Put#(Bool) statsEn_put; | |
51 | |
52 // Interface for collecting statistics | |
53 interface DCacheStats stats; | |
54 | |
55 endinterface | |
56 | |
57 | |
58 //---------------------------------------------------------------------- | |
59 // Cache Types | |
60 //---------------------------------------------------------------------- | |
61 | |
62 typedef 10 CacheLineIndexSz; | |
63 typedef 20 CacheLineTagSz; | |
64 typedef 32 CacheLineSz; | |
65 | |
66 typedef Bit#(CacheLineIndexSz) CacheLineIndex; | |
67 typedef Bit#(CacheLineTagSz) CacheLineTag; | |
68 typedef Bit#(CacheLineSz) CacheLine; | |
69 | |
70 typedef enum | |
71 { | |
72 Init, | |
73 Access, | |
74 RefillReq, | |
75 RefillResp | |
76 } | |
77 CacheStage | |
78 deriving (Eq,Bits); | |
79 | |
80 //---------------------------------------------------------------------- | |
81 // Helper functions | |
82 //---------------------------------------------------------------------- | |
83 | |
84 function Bit#(AddrSz) getAddr( DataReq req ); | |
85 | |
86 Bit#(AddrSz) addr = ?; | |
87 case ( req ) matches | |
88 tagged LoadReq .ld : addr = ld.addr; | |
89 tagged StoreReq .st : addr = st.addr; | |
90 endcase | |
91 | |
92 return addr; | |
93 | |
94 endfunction | |
95 | |
96 function CacheLineIndex getCacheLineIndex( DataReq req ); | |
97 Bit#(AddrSz) addr = getAddr(req); | |
98 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 ); | |
99 return index; | |
100 endfunction | |
101 | |
102 function CacheLineTag getCacheLineTag( DataReq req ); | |
103 Bit#(AddrSz) addr = getAddr(req); | |
104 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 ); | |
105 return tag; | |
106 endfunction | |
107 | |
108 function Bit#(AddrSz) getCacheLineAddr( DataReq req ); | |
109 Bit#(AddrSz) addr = getAddr(req); | |
110 return ((addr >> 2) << 2); | |
111 endfunction | |
112 | |
113 //---------------------------------------------------------------------- | |
114 // Main module | |
115 //---------------------------------------------------------------------- | |
116 | |
117 (* doc = "synthesis attribute ram_style mkDataCache distributed;" *) | |
118 (* synthesize *) | |
119 module mkDataCache( DCache#(DataReq,DataResp) ); | |
120 | |
121 //----------------------------------------------------------- | |
122 // State | |
123 | |
124 Reg#(CacheStage) stage <- mkReg(Init); | |
125 | |
126 RegFile#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkRegFileFull(); | |
127 RegFile#(CacheLineIndex,CacheLine) cacheDataRam <- mkRegFileFull(); | |
128 | |
129 FIFO#(DataReq) reqQ <- mkFIFO(); | |
130 FIFOF#(DataResp) respQ <- mkBFIFOF1(); | |
131 | |
132 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1(); | |
133 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO(); | |
134 | |
135 Reg#(CacheLineIndex) initCounter <- mkReg(1); | |
136 | |
137 // Statistics state | |
138 | |
139 Reg#(Bool) statsEn <- mkReg(False); | |
140 | |
141 Reg#(Stat) num_accesses <- mkReg(0); | |
142 Reg#(Stat) num_misses <- mkReg(0); | |
143 Reg#(Stat) num_writebacks <- mkReg(0); | |
144 | |
145 //----------------------------------------------------------- | |
146 // Name some wires | |
147 | |
148 let req = reqQ.first(); | |
149 let reqIndex = getCacheLineIndex(req); | |
150 let reqTag = getCacheLineTag(req); | |
151 let reqCacheLineAddr = getCacheLineAddr(req); | |
152 | |
153 //----------------------------------------------------------- | |
154 // Initialize | |
155 | |
156 rule init ( stage == Init ); | |
157 traceTiny("mkDataCacheBlocking", "stage","i"); | |
158 initCounter <= initCounter + 1; | |
159 cacheTagRam.upd(initCounter,Invalid); | |
160 if ( initCounter == 0 ) | |
161 stage <= Access; | |
162 endrule | |
163 | |
164 //----------------------------------------------------------- | |
165 // Access cache rule | |
166 | |
167 rule access ( (stage == Access) && respQ.notFull() ); | |
168 | |
169 // Statistics | |
170 | |
171 if ( statsEn ) | |
172 num_accesses <= num_accesses + 1; | |
173 | |
174 | |
175 // Get the corresponding tag from the rams | |
176 | |
177 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); | |
178 | |
179 // Handle cache hits ... | |
180 | |
181 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) ) | |
182 begin | |
183 traceTiny("mkDataCacheBlocking", "hitMiss","h"); | |
184 reqQ.deq(); | |
185 | |
186 case ( req ) matches | |
187 | |
188 tagged LoadReq .ld : | |
189 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } ); | |
190 | |
191 tagged StoreReq .st : | |
192 begin | |
193 respQ.enq( StoreResp { tag : st.tag } ); | |
194 cacheDataRam.upd(reqIndex,st.data); | |
195 end | |
196 | |
197 endcase | |
198 | |
199 end | |
200 | |
201 // Handle cache misses ... | |
202 | |
203 else | |
204 begin | |
205 traceTiny("mkDataCacheBlocking", "hitMiss","m"); | |
206 if ( statsEn ) | |
207 num_misses <= num_misses + 1; | |
208 | |
209 // Currently we don't use dirty bits so we always writeback the data if it is valid | |
210 | |
211 if ( isValid(cacheLineTag) ) | |
212 begin | |
213 | |
214 if ( statsEn ) | |
215 num_writebacks <= num_writebacks + 1; | |
216 | |
217 MainMemReq wbReq | |
218 = StoreReq { tag : 0, | |
219 addr : { unJust(cacheLineTag), reqIndex, 2'b0 }, | |
220 data : cacheDataRam.sub(reqIndex) }; | |
221 | |
222 mainMemReqQ.enq(wbReq); | |
223 stage <= RefillReq; | |
224 end | |
225 | |
226 // Otherwise we can issue the refill request now | |
227 | |
228 else | |
229 begin | |
230 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); | |
231 stage <= RefillResp; | |
232 end | |
233 | |
234 end | |
235 | |
236 endrule | |
237 | |
238 //----------------------------------------------------------- | |
239 // Refill request rule | |
240 | |
241 rule refillReq ( stage == RefillReq ); | |
242 traceTiny("mkDataCacheBlocking", "stage","r"); | |
243 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } ); | |
244 stage <= RefillResp; | |
245 endrule | |
246 | |
247 //----------------------------------------------------------- | |
248 // Refill response rule | |
249 | |
250 rule refillResp ( stage == RefillResp ); | |
251 traceTiny("mkDataCacheBlocking", "stage","R"); | |
252 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first()); | |
253 | |
254 // Write the new data into the cache and update the tag | |
255 | |
256 mainMemRespQ.deq(); | |
257 case ( mainMemRespQ.first() ) matches | |
258 | |
259 tagged LoadResp .ld : | |
260 begin | |
261 cacheTagRam.upd(reqIndex,Valid(reqTag)); | |
262 cacheDataRam.upd(reqIndex,ld.data); | |
263 end | |
264 | |
265 tagged StoreResp .st : | |
266 noAction; | |
267 | |
268 endcase | |
269 | |
270 stage <= Access; | |
271 endrule | |
272 | |
273 //----------------------------------------------------------- | |
274 // Methods | |
275 | |
276 interface Client mmem_client; | |
277 interface Get request = toGet(mainMemReqQ); | |
278 interface Put response = toPut(mainMemRespQ); | |
279 endinterface | |
280 | |
281 interface Server proc_server; | |
282 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",toPut(reqQ)); | |
283 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",toGet(respQ)); | |
284 endinterface | |
285 | |
286 interface Put statsEn_put = toPut(asReg(statsEn)); | |
287 | |
288 interface DCacheStats stats; | |
289 interface Get num_accesses = toGet(asReg(num_accesses)); | |
290 interface Get num_misses = toGet(asReg(num_misses)); | |
291 interface Get num_writebacks = toGet(asReg(num_writebacks)); | |
292 endinterface | |
293 | |
294 endmodule | |
295 |