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comparison core/src/BranchPred.bsv @ 1:91a1f76ddd62 pygar svn.2

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[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
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0:6d1ff93e3afa 1:91a1f76ddd62
1 import RegFile::*;
2 import ProcTypes::*;
3 import FIFO::*;
4
5 typedef Maybe#(Addr) BrPred;
6 typedef Bit#(4) BPindx;
7
8 typedef struct {Addr brpc; Addr nextpc;} BrPair deriving (Bits,Eq);
9
10 typedef union tagged
11 {
12 BrPair Valid;
13 void Invalid;
14 } CBranchPath deriving(Bits, Eq); // have the cache start out invalid and add valid values.
15
16 interface BranchPred;
17 method BrPred get(Addr pres); //returns a maybe type that is invalid if no predition
18 method Action upd(Addr pres, Addr next);
19 endinterface
20
21 module mkBranchPred(BranchPred);
22
23 //state variables
24 RegFile#(BPindx, CBranchPath) bcache <- mkRegFileFull(); // cache to hold 16 (based on BPindx)
25
26 method Action upd(Addr pres, Addr next);
27 BrPair brp;
28 brp = BrPair {brpc:pres, nextpc:next};
29 bcache.upd(pres[5:2], tagged Valid brp);
30 endmethod
31
32 method BrPred get(Addr prespc);
33 BPindx rd = prespc[5:2];
34 let cbp = bcache.sub(rd);
35 if (cbp matches tagged Valid .bp &&& bp.brpc == prespc) //make sure that the read value was actually put there and the full address matches
36 return tagged Valid bp.nextpc;
37 else return Invalid;
38 endmethod
39
40 endmodule
41