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comparison core/sim/bdir_dut/SceMiLayer.bi @ 1:91a1f76ddd62 pygar svn.2

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[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
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0:6d1ff93e3afa 1:91a1f76ddd62
1 signature SceMiLayer where {
2 import ¶Assert®¶;
3
4 import ¶ConfigReg®¶;
5
6 import ¶Counter®¶;
7
8 import ¶DReg®¶;
9
10 import ¶EdgeDetect®¶;
11
12 import ¶FIFOF_®¶;
13
14 import ¶FIFOF®¶;
15
16 import ¶FIFO®¶;
17
18 import ¶HList®¶;
19
20 import ¶Inout®¶;
21
22 import ¶List®¶;
23
24 import BFIFO;
25
26 import ¶Clocks®¶;
27
28 import ¶DiniPCIE®¶;
29
30 import ¶ListN®¶;
31
32 import ¶ModuleContextCore®¶;
33
34 import ¶ModuleContext®¶;
35
36 import ¶Monad®¶;
37
38 import ¶PrimArray®¶;
39
40 import ¶RWire®¶;
41
42 import ¶RegFile®¶;
43
44 import ¶Real®¶;
45
46 import ¶RevertingVirtualReg®¶;
47
48 import ¶Reserved®¶;
49
50 import SFIFO;
51
52 import ¶Vector®¶;
53
54 import ¶BRAMCore®¶;
55
56 import ¶BUtils®¶;
57
58 import ¶Connectable®¶;
59
60 import ¶DefaultValue®¶;
61
62 import ¶Gearbox®¶;
63
64 import ¶GetPut®¶;
65
66 import ¶AlignedFIFOs®¶;
67
68 import ¶ClientServer®¶;
69
70 import ¶FIFOLevel®¶;
71
72 import ¶SceMiDefines®¶;
73
74 import ¶SceMiProxies®¶;
75
76 import ¶SpecialFIFOs®¶;
77
78 import ¶SceMiInternals®¶;
79
80 import ¶SceMiAldecMacros®¶;
81
82 import ¶SceMiEveMacros®¶;
83
84 import ¶SceMiMacros®¶;
85
86 import ¶TieOff®¶;
87
88 import Trace;
89
90 import MemTypes;
91
92 import MemArb;
93
94 import ProcTypes;
95
96 import BRegFile;
97
98 import BranchPred;
99
100 import DataCacheBlocking;
101
102 import InstCacheBlocking;
103
104 import Processor;
105
106 import Core;
107
108 import ¶UnitAppendList®¶;
109
110 import ¶XilinxCells®¶;
111
112 import ¶SceMiClocks®¶;
113
114 import ¶SceMiDiniPCIE®¶;
115
116 import ¶SceMiTCP®¶;
117
118 import ¶XilinxPCIE®¶;
119
120 import ¶SceMiVirtex5PCIE®¶;
121
122 import ¶SceMiPCIE®¶;
123
124 import ¶SceMiCore®¶;
125
126 import ¶SceMiXactors®¶;
127
128 import ¶SceMiSerialProbe®¶;
129
130 import ¶SceMi®¶;
131
132 interface (SceMiLayer.DutWrapper :: *) = {
133 SceMiLayer.core :: Core.Core;
134 SceMiLayer.doreset :: ¶GetPut®¶.¶Put®¶ (¶Prelude®¶.¶Bit®¶ 1)
135 };
136
137 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.DutWrapper;
138
139 instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.DutWrapper;
140
141 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.DutWrapper;
142
143 SceMiLayer.mkDutWrapper :: ¶Prelude®¶.¶Module®¶ SceMiLayer.DutWrapper;
144
145 SceMiLayer.mkSceMiLayer :: ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶;
146
147 SceMiLayer.mkCPUToHostXactor :: Processor.CPUToHost ->
148 ¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ ->
149 ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶;
150
151 data (SceMiLayer.StatID :: *) =
152 SceMiLayer.DCACHE_ACCESSES () |
153 SceMiLayer.DCACHE_MISSES () |
154 SceMiLayer.DCACHE_WRITEBACKS () |
155 SceMiLayer.ICACHE_ACCESSES () |
156 SceMiLayer.ICACHE_MISSES () |
157 SceMiLayer.ICACHE_EVICTIONS () |
158 SceMiLayer.PROC_INST () |
159 SceMiLayer.PROC_CYCLES ();
160
161 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUndefined®¶ SceMiLayer.StatID;
162
163 instance SceMiLayer ¶Prelude®¶.¶PrimDeepSeqCond®¶ SceMiLayer.StatID;
164
165 instance SceMiLayer ¶Prelude®¶.¶PrimMakeUninitialized®¶ SceMiLayer.StatID;
166
167 instance SceMiLayer ¶Prelude®¶.¶Bits®¶ SceMiLayer.StatID 3;
168
169 instance SceMiLayer ¶Prelude®¶.¶Eq®¶ SceMiLayer.StatID;
170
171 SceMiLayer.mkCoreStatsXactor :: Core.CoreStats ->
172 ¶SceMiDefines®¶.¶SceMiClockPortIfc®¶ ->
173 ¶SceMiInternals®¶.¶SceMiModule®¶ ¶Prelude®¶.¶Empty®¶
174 }