comparison core/sim/bdir_dut/Processor.bi @ 1:91a1f76ddd62 pygar svn.2

[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
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0:6d1ff93e3afa 1:91a1f76ddd62
1 signature Processor where {
2 import ¶Assert®¶;
3
4 import ¶ConfigReg®¶;
5
6 import ¶Counter®¶;
7
8 import ¶FIFOF_®¶;
9
10 import ¶FIFOF®¶;
11
12 import ¶FIFO®¶;
13
14 import ¶Inout®¶;
15
16 import ¶List®¶;
17
18 import BFIFO;
19
20 import ¶Clocks®¶;
21
22 import ¶ListN®¶;
23
24 import ¶Monad®¶;
25
26 import ¶PrimArray®¶;
27
28 import ¶RWire®¶;
29
30 import ¶RegFile®¶;
31
32 import SFIFO;
33
34 import ¶Vector®¶;
35
36 import ¶Connectable®¶;
37
38 import ¶GetPut®¶;
39
40 import ¶ClientServer®¶;
41
42 import Trace;
43
44 import MemTypes;
45
46 import ProcTypes;
47
48 import BRegFile;
49
50 import BranchPred;
51
52 interface (Processor.ProcStats :: *) = {
53 Processor.num_cycles :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;
54 Processor.num_inst :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat
55 };
56
57 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.ProcStats;
58
59 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.ProcStats;
60
61 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.ProcStats;
62
63 interface (Processor.CPUToHost :: *) = {
64 Processor.cpuToHost :: ¶Prelude®¶.¶Int®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [req] #-}
65 };
66
67 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.CPUToHost;
68
69 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.CPUToHost;
70
71 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.CPUToHost;
72
73 interface (Processor.Proc :: *) = {
74 Processor.dmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.DataReq MemTypes.DataResp;
75 Processor.imem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.InstReq MemTypes.InstResp;
76 Processor.statsEn_get :: ¶GetPut®¶.¶Get®¶ ¶Prelude®¶.¶Bool®¶;
77 Processor.stats :: Processor.ProcStats;
78 Processor.tohost :: Processor.CPUToHost
79 };
80
81 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.Proc;
82
83 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.Proc;
84
85 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.Proc;
86
87 data (Processor.Stage :: *) = Processor.PCgen () | Processor.Exec () | Processor.Writeback ();
88
89 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.Stage;
90
91 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.Stage;
92
93 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.Stage;
94
95 instance Processor ¶Prelude®¶.¶Eq®¶ Processor.Stage;
96
97 instance Processor ¶Prelude®¶.¶Bits®¶ Processor.Stage 2;
98
99 interface (Processor.BRFile :: *) = {
100 Processor.wr :: ProcTypes.Rindx ->
101 ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [rindx, ¡data¡] #-};
102 Processor.rd1 :: ProcTypes.Rindx -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [rindx] #-};
103 Processor.rd2 :: ProcTypes.Rindx -> ¶Prelude®¶.¶Bit®¶ 32 {-# arg_names = [rindx] #-}
104 };
105
106 instance Processor ¶Prelude®¶.¶PrimMakeUndefined®¶ Processor.BRFile;
107
108 instance Processor ¶Prelude®¶.¶PrimDeepSeqCond®¶ Processor.BRFile;
109
110 instance Processor ¶Prelude®¶.¶PrimMakeUninitialized®¶ Processor.BRFile;
111
112 Processor.mkBRFile :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Processor.BRFile;
113
114 Processor.slt :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32;
115
116 Processor.sltu :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32;
117
118 Processor.rshft :: ¶Prelude®¶.¶Bit®¶ 32 -> ¶Prelude®¶.¶Bit®¶ 32;
119
120 Processor.findwbf :: ProcTypes.Rindx -> ProcTypes.WBResult -> ¶Prelude®¶.¶Bool®¶;
121
122 Processor.stall :: ProcTypes.Instr ->
123 SFIFO.SFIFO ProcTypes.WBResult ProcTypes.Rindx -> ¶Prelude®¶.¶Bool®¶;
124
125 Processor.mkProc :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ Processor.Proc
126 }