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comparison core/sim/bdir_dut/MemArb.bi @ 1:91a1f76ddd62 pygar svn.2

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[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
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0:6d1ff93e3afa 1:91a1f76ddd62
1 signature MemArb where {
2 import ¶Assert®¶;
3
4 import ¶Counter®¶;
5
6 import ¶FIFOF_®¶;
7
8 import ¶FIFOF®¶;
9
10 import ¶FIFO®¶;
11
12 import ¶Inout®¶;
13
14 import ¶List®¶;
15
16 import BFIFO;
17
18 import ¶Clocks®¶;
19
20 import ¶ListN®¶;
21
22 import ¶PrimArray®¶;
23
24 import ¶Vector®¶;
25
26 import ¶Connectable®¶;
27
28 import ¶GetPut®¶;
29
30 import ¶ClientServer®¶;
31
32 import Trace;
33
34 import MemTypes;
35
36 interface (MemArb.MemArb :: *) = {
37 MemArb.cache0_server :: ¶ClientServer®¶.¶Server®¶ MemTypes.MainMemReq MemTypes.MainMemResp;
38 MemArb.cache1_server :: ¶ClientServer®¶.¶Server®¶ MemTypes.MainMemReq MemTypes.MainMemResp;
39 MemArb.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp
40 };
41
42 instance MemArb ¶Prelude®¶.¶PrimMakeUndefined®¶ MemArb.MemArb;
43
44 instance MemArb ¶Prelude®¶.¶PrimDeepSeqCond®¶ MemArb.MemArb;
45
46 instance MemArb ¶Prelude®¶.¶PrimMakeUninitialized®¶ MemArb.MemArb;
47
48 data (MemArb.ReqPtr :: *) = MemArb.REQ0 () | MemArb.REQ1 ();
49
50 instance MemArb ¶Prelude®¶.¶PrimMakeUndefined®¶ MemArb.ReqPtr;
51
52 instance MemArb ¶Prelude®¶.¶PrimDeepSeqCond®¶ MemArb.ReqPtr;
53
54 instance MemArb ¶Prelude®¶.¶PrimMakeUninitialized®¶ MemArb.ReqPtr;
55
56 instance MemArb ¶Prelude®¶.¶Eq®¶ MemArb.ReqPtr;
57
58 instance MemArb ¶Prelude®¶.¶Bits®¶ MemArb.ReqPtr 1;
59
60 MemArb.mkMemArb :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ MemArb.MemArb
61 }