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comparison core/sim/bdir_dut/InstCacheBlocking.bi @ 1:91a1f76ddd62 pygar svn.2

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[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
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0:6d1ff93e3afa 1:91a1f76ddd62
1 signature InstCacheBlocking where {
2 import ¶Assert®¶;
3
4 import ¶Counter®¶;
5
6 import ¶FIFOF_®¶;
7
8 import ¶FIFOF®¶;
9
10 import ¶FIFO®¶;
11
12 import ¶Inout®¶;
13
14 import ¶List®¶;
15
16 import BFIFO;
17
18 import ¶Clocks®¶;
19
20 import ¶ListN®¶;
21
22 import ¶PrimArray®¶;
23
24 import ¶RWire®¶;
25
26 import ¶RegFile®¶;
27
28 import ¶Vector®¶;
29
30 import ¶Connectable®¶;
31
32 import ¶GetPut®¶;
33
34 import ¶ClientServer®¶;
35
36 import Trace;
37
38 import MemTypes;
39
40 import ProcTypes;
41
42 interface (InstCacheBlocking.ICacheStats :: *) = {
43 InstCacheBlocking.num_accesses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;
44 InstCacheBlocking.num_misses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;
45 InstCacheBlocking.num_evictions :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat
46 };
47
48 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ InstCacheBlocking.ICacheStats;
49
50 instance InstCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ InstCacheBlocking.ICacheStats;
51
52 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ InstCacheBlocking.ICacheStats;
53
54 interface (InstCacheBlocking.ICache :: * -> * -> *) req_t resp_t = {
55 InstCacheBlocking.proc_server :: ¶ClientServer®¶.¶Server®¶ req_t resp_t;
56 InstCacheBlocking.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp;
57 InstCacheBlocking.statsEn_put :: ¶GetPut®¶.¶Put®¶ ¶Prelude®¶.¶Bool®¶;
58 InstCacheBlocking.stats :: InstCacheBlocking.ICacheStats
59 };
60
61 instance InstCacheBlocking (¶Prelude®¶.¶PrimMakeUndefined®¶ resp_t) =>
62 ¶Prelude®¶.¶PrimMakeUndefined®¶ (InstCacheBlocking.ICache req_t resp_t);
63
64 instance InstCacheBlocking (¶Prelude®¶.¶PrimDeepSeqCond®¶ resp_t) =>
65 ¶Prelude®¶.¶PrimDeepSeqCond®¶ (InstCacheBlocking.ICache req_t resp_t);
66
67 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶
68 (InstCacheBlocking.ICache req_t resp_t);
69
70 type (InstCacheBlocking.CacheLineIndexSz :: #) = 10;
71
72 type (InstCacheBlocking.CacheLineTagSz :: #) = 20;
73
74 type (InstCacheBlocking.CacheLineSz :: #) = 32;
75
76 type (InstCacheBlocking.CacheLineIndex :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineIndexSz;
77
78 type (InstCacheBlocking.CacheLineTag :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineTagSz;
79
80 type (InstCacheBlocking.CacheLine :: *) = ¶Prelude®¶.¶Bit®¶ InstCacheBlocking.CacheLineSz;
81
82 data (InstCacheBlocking.CacheStage :: *) =
83 InstCacheBlocking.Init () |
84 InstCacheBlocking.Access () |
85 InstCacheBlocking.Evict () |
86 InstCacheBlocking.RefillReq () |
87 InstCacheBlocking.RefillResp ();
88
89 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ InstCacheBlocking.CacheStage;
90
91 instance InstCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ InstCacheBlocking.CacheStage;
92
93 instance InstCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ InstCacheBlocking.CacheStage;
94
95 instance InstCacheBlocking ¶Prelude®¶.¶Eq®¶ InstCacheBlocking.CacheStage;
96
97 instance InstCacheBlocking ¶Prelude®¶.¶Bits®¶ InstCacheBlocking.CacheStage 3;
98
99 InstCacheBlocking.getAddr :: MemTypes.InstReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz;
100
101 InstCacheBlocking.getCacheLineIndex :: MemTypes.InstReq -> InstCacheBlocking.CacheLineIndex;
102
103 InstCacheBlocking.getCacheLineTag :: MemTypes.InstReq -> InstCacheBlocking.CacheLineTag;
104
105 InstCacheBlocking.getCacheLineAddr :: MemTypes.InstReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz;
106
107 InstCacheBlocking.mkInstCache :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>
108 _m__ (InstCacheBlocking.ICache MemTypes.InstReq MemTypes.InstResp)
109 }