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comparison core/sim/bdir_dut/DataCacheBlocking.bi @ 1:91a1f76ddd62 pygar svn.2

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[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
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0:6d1ff93e3afa 1:91a1f76ddd62
1 signature DataCacheBlocking where {
2 import ¶Assert®¶;
3
4 import ¶Counter®¶;
5
6 import ¶FIFOF_®¶;
7
8 import ¶FIFOF®¶;
9
10 import ¶FIFO®¶;
11
12 import ¶Inout®¶;
13
14 import ¶List®¶;
15
16 import BFIFO;
17
18 import ¶Clocks®¶;
19
20 import ¶ListN®¶;
21
22 import ¶PrimArray®¶;
23
24 import ¶RegFile®¶;
25
26 import ¶Vector®¶;
27
28 import ¶Connectable®¶;
29
30 import ¶GetPut®¶;
31
32 import ¶ClientServer®¶;
33
34 import Trace;
35
36 import MemTypes;
37
38 import ProcTypes;
39
40 interface (DataCacheBlocking.DCacheStats :: *) = {
41 DataCacheBlocking.num_accesses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;
42 DataCacheBlocking.num_misses :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat;
43 DataCacheBlocking.num_writebacks :: ¶GetPut®¶.¶Get®¶ ProcTypes.Stat
44 };
45
46 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ DataCacheBlocking.DCacheStats;
47
48 instance DataCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ DataCacheBlocking.DCacheStats;
49
50 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ DataCacheBlocking.DCacheStats;
51
52 interface (DataCacheBlocking.DCache :: * -> * -> *) req_t resp_t = {
53 DataCacheBlocking.proc_server :: ¶ClientServer®¶.¶Server®¶ req_t resp_t;
54 DataCacheBlocking.mmem_client :: ¶ClientServer®¶.¶Client®¶ MemTypes.MainMemReq MemTypes.MainMemResp;
55 DataCacheBlocking.statsEn_put :: ¶GetPut®¶.¶Put®¶ ¶Prelude®¶.¶Bool®¶;
56 DataCacheBlocking.stats :: DataCacheBlocking.DCacheStats
57 };
58
59 instance DataCacheBlocking (¶Prelude®¶.¶PrimMakeUndefined®¶ resp_t) =>
60 ¶Prelude®¶.¶PrimMakeUndefined®¶ (DataCacheBlocking.DCache req_t resp_t);
61
62 instance DataCacheBlocking (¶Prelude®¶.¶PrimDeepSeqCond®¶ resp_t) =>
63 ¶Prelude®¶.¶PrimDeepSeqCond®¶ (DataCacheBlocking.DCache req_t resp_t);
64
65 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶
66 (DataCacheBlocking.DCache req_t resp_t);
67
68 type (DataCacheBlocking.CacheLineIndexSz :: #) = 10;
69
70 type (DataCacheBlocking.CacheLineTagSz :: #) = 20;
71
72 type (DataCacheBlocking.CacheLineSz :: #) = 32;
73
74 type (DataCacheBlocking.CacheLineIndex :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineIndexSz;
75
76 type (DataCacheBlocking.CacheLineTag :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineTagSz;
77
78 type (DataCacheBlocking.CacheLine :: *) = ¶Prelude®¶.¶Bit®¶ DataCacheBlocking.CacheLineSz;
79
80 data (DataCacheBlocking.CacheStage :: *) =
81 DataCacheBlocking.Init () |
82 DataCacheBlocking.Access () |
83 DataCacheBlocking.RefillReq () |
84 DataCacheBlocking.RefillResp ();
85
86 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUndefined®¶ DataCacheBlocking.CacheStage;
87
88 instance DataCacheBlocking ¶Prelude®¶.¶PrimDeepSeqCond®¶ DataCacheBlocking.CacheStage;
89
90 instance DataCacheBlocking ¶Prelude®¶.¶PrimMakeUninitialized®¶ DataCacheBlocking.CacheStage;
91
92 instance DataCacheBlocking ¶Prelude®¶.¶Eq®¶ DataCacheBlocking.CacheStage;
93
94 instance DataCacheBlocking ¶Prelude®¶.¶Bits®¶ DataCacheBlocking.CacheStage 2;
95
96 DataCacheBlocking.getAddr :: MemTypes.DataReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz;
97
98 DataCacheBlocking.getCacheLineIndex :: MemTypes.DataReq -> DataCacheBlocking.CacheLineIndex;
99
100 DataCacheBlocking.getCacheLineTag :: MemTypes.DataReq -> DataCacheBlocking.CacheLineTag;
101
102 DataCacheBlocking.getCacheLineAddr :: MemTypes.DataReq -> ¶Prelude®¶.¶Bit®¶ MemTypes.AddrSz;
103
104 DataCacheBlocking.mkDataCache :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>
105 _m__ (DataCacheBlocking.DCache MemTypes.DataReq MemTypes.DataResp)
106 }