pygar: core/sim/bdir_dut/Bridge.bi comparison

comparison core/sim/bdir_dut/Bridge.bi @ 1:91a1f76ddd62 pygar svn.2

[svn r2] Adding initial lab 5 source

author	punk
date	Tue, 13 Apr 2010 17:34:33 -0400
parents
children

comparison

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-:6d1ff93e3afa
+:91a1f76ddd62
+signature Bridge where {
+import 詛ssert振;
+import 詆onfigReg振;
+import 詆ounter振;
+import 訴Reg振;
+import 診dgeDetect振;
+import 訶IFOF_振;
+import 訶IFOF振;
+import 訶IFO振;
+import 象List振;
+import 貂nout振;
+import 貳ist振;
+import BFIFO;
+import 詆locks振;
+import 訴iniPCIE振;
+import 貳istN振;
+import 貽oduleContextCore振;
+import 貽oduleContext振;
+import 貽onad振;
+import 賀rimArray振;
+import 買Wire振;
+import 買egFile振;
+import 買eal振;
+import 買evertingVirtualReg振;
+import 買eserved振;
+import SFIFO;
+import 越ector振;
+import 詐RAMCore振;
+import 詐Utils振;
+import 詆onnectable振;
+import 訴efaultValue振;
+import 詖earbox振;
+import 詖etPut振;
+import 詛lignedFIFOs振;
+import 詆lientServer振;
+import 訶IFOLevel振;
+import 貶ceMiDefines振;
+import 貶ceMiProxies振;
+import 貶pecialFIFOs振;
+import 貶ceMiInternals振;
+import 貶ceMiAldecMacros振;
+import 貶ceMiEveMacros振;
+import 貶ceMiMacros振;
+import 貿ieOff振;
+import Trace;
+import MemTypes;
+import MemArb;
+import ProcTypes;
+import BRegFile;
+import BranchPred;
+import DataCacheBlocking;
+import InstCacheBlocking;
+import Processor;
+import Core;
+import 貸nitAppendList振;
+import 趁ilinxCells振;
+import 貶ceMiClocks振;
+import 貶ceMiDiniPCIE振;
+import 貶ceMiTCP振;
+import 趁ilinxPCIE振;
+import 貶ceMiVirtex5PCIE振;
+import 貶ceMiPCIE振;
+import 貶ceMiCore振;
+import 貶ceMiXactors振;
+import 貶ceMiSerialProbe振;
+import 貶ceMi振;
+import SceMiLayer;
+Bridge.lt :: 貶ceMiDefines振.貶ceMiLinkType振;
+Bridge.mkBridge :: (賀relude振.貂sModule振 _m__ _c__) => _m__ 賀relude振.診mpty振
+}

Mercurial > pygar

comparison core/sim/bdir_dut/Bridge.bi @ 1:91a1f76ddd62 pygar svn.2