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comparison core/sim/bdir_dut/BRegFile.bi @ 1:91a1f76ddd62 pygar svn.2

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[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
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0:6d1ff93e3afa 1:91a1f76ddd62
1 signature BRegFile where {
2 import ¶Counter®¶;
3
4 import ¶FIFOF_®¶;
5
6 import ¶FIFOF®¶;
7
8 import ¶FIFO®¶;
9
10 import ¶Inout®¶;
11
12 import ¶List®¶;
13
14 import ¶Clocks®¶;
15
16 import ¶ListN®¶;
17
18 import ¶PrimArray®¶;
19
20 import ¶RWire®¶;
21
22 import ¶RegFile®¶;
23
24 import ¶Vector®¶;
25
26 import ¶Connectable®¶;
27
28 import ¶GetPut®¶;
29
30 import ¶ClientServer®¶;
31
32 import Trace;
33
34 import ProcTypes;
35
36 interface (BRegFile.BRegFile :: * -> * -> *) index_t data_t = {
37 BRegFile.upd :: index_t -> data_t -> ¶Prelude®¶.¶Action®¶ {-# arg_names = [addr, ¡data¡] #-};
38 BRegFile.sub :: index_t -> data_t {-# arg_names = [addr] #-}
39 };
40
41 instance BRegFile (¶Prelude®¶.¶PrimMakeUndefined®¶ data_t) =>
42 ¶Prelude®¶.¶PrimMakeUndefined®¶ (BRegFile.BRegFile index_t data_t);
43
44 instance BRegFile ¶Prelude®¶.¶PrimDeepSeqCond®¶ (BRegFile.BRegFile index_t data_t);
45
46 instance BRegFile ¶Prelude®¶.¶PrimMakeUninitialized®¶ (BRegFile.BRegFile index_t data_t);
47
48 BRegFile.mkBRegFile :: (¶Prelude®¶.¶Bounded®¶ index_t,
49 ¶Prelude®¶.¶Eq®¶ index_t,
50 ¶Prelude®¶.¶Bits®¶ data_t size_data,
51 ¶Prelude®¶.¶Bits®¶ index_t size_index,
52 ¶Prelude®¶.¶IsModule®¶ _m__ _c__) =>
53 _m__ (¶RegFile®¶.¶RegFile®¶ index_t data_t)
54 }