Mercurial > pygar

comparison common/ProcTypes.bsv @ 1:91a1f76ddd62 pygar svn.2

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
[svn r2] Adding initial lab 5 source
author punk
date Tue, 13 Apr 2010 17:34:33 -0400
parents
children
comparison
equal deleted inserted replaced
0:6d1ff93e3afa 1:91a1f76ddd62
1
2 import Trace::*;
3
4 //----------------------------------------------------------------------
5 // Other typedefs
6 //----------------------------------------------------------------------
7
8 typedef Bit#(32) Addr;
9 typedef Int#(18) Stat;
10
11 //----------------------------------------------------------------------
12 // Basic instruction type
13 //----------------------------------------------------------------------
14
15 typedef Bit#(5) Rindx;
16 typedef Bit#(16) Simm;
17 typedef Bit#(16) Zimm;
18 typedef Bit#(8) Epoch;
19 typedef Bit#(5) Shamt;
20 typedef Bit#(26) Target;
21 typedef Bit#(5) CP0indx;
22 typedef Bit#(32) Data;
23
24 typedef enum
25 {
26 Taken,
27 NotTaken
28 }
29 Direction
30 deriving(Bits,Eq);
31
32
33 //----------------------------------------------------------------------
34 // Pipeline typedefs
35 //----------------------------------------------------------------------
36
37 typedef union tagged
38 {
39 Tuple2#(Rindx,Data) ALUWB;
40 Rindx MemWB;
41 Tuple2#(Rindx,Data) CoWB;
42 }
43 WritebackType
44 deriving(Bits,Eq);
45
46 ////////////////////////
47 // I Add Writeback queue type
48 ////////////
49 typedef union tagged
50 {
51 struct {Bit#(32) data; Rindx dest; } WB_ALU;
52 Bit#(32) WB_Host;
53 Rindx WB_Load;
54 void WB_Store;
55 }
56 WBResult deriving(Eq, Bits);
57
58 //typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
59 typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
60
61 typedef union tagged
62 {
63
64 struct { Rindx rbase; Rindx rdst; Simm offset; } LW;
65 struct { Rindx rbase; Rindx rsrc; Simm offset; } SW;
66
67 struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU;
68 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI;
69 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU;
70 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI;
71 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI;
72 struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI;
73 struct { Rindx rdst; Zimm imm; } LUI;
74
75 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL;
76 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL;
77 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA;
78 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV;
79 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV;
80 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV;
81 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU;
82 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU;
83 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND;
84 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR;
85 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR;
86 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR;
87 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT;
88 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU;
89
90 struct { Target target; } J;
91 struct { Target target; } JAL;
92 struct { Rindx rsrc; } JR;
93 struct { Rindx rsrc; Rindx rdst; } JALR;
94 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ;
95 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE;
96 struct { Rindx rsrc; Simm offset; } BLEZ;
97 struct { Rindx rsrc; Simm offset; } BGTZ;
98 struct { Rindx rsrc; Simm offset; } BLTZ;
99 struct { Rindx rsrc; Simm offset; } BGEZ;
100
101 struct { Rindx rdst; CP0indx cop0src; } MFC0;
102 struct { Rindx rsrc; CP0indx cop0dst; } MTC0;
103
104 void ILLEGAL;
105
106 }
107 Instr deriving(Eq);
108
109 //----------------------------------------------------------------------
110 // Pack and Unpack
111 //----------------------------------------------------------------------
112
113 Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000;
114 Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010;
115 Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011;
116 Bit#(6) fcSLLV = 6'b000100;
117 Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110;
118 Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111;
119 Bit#(6) fcADDU = 6'b100001;
120 Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011;
121 Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100;
122 Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101;
123 Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110;
124 Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111;
125 Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010;
126 Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011;
127
128 Bit#(6) opJ = 6'b000010;
129 Bit#(6) opJAL = 6'b000011;
130 Bit#(6) fcJR = 6'b001000;
131 Bit#(6) fcJALR = 6'b001001;
132 Bit#(6) opBEQ = 6'b000100;
133 Bit#(6) opBNE = 6'b000101;
134 Bit#(6) opBLEZ = 6'b000110;
135 Bit#(6) opBGTZ = 6'b000111;
136 Bit#(5) rtBLTZ = 5'b00000;
137 Bit#(5) rtBGEZ = 5'b00001;
138
139 Bit#(5) rsMFC0 = 5'b00000;
140 Bit#(5) rsMTC0 = 5'b00100;
141
142 instance Bits#(Instr,32);
143
144 // Pack Function
145
146 function Bit#(32) pack( Instr instr );
147
148 case ( instr ) matches
149
150 tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset };
151 tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset };
152
153 tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm };
154 tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm };
155 tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm };
156 tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm };
157 tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm };
158 tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm };
159 tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm };
160
161 tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL };
162 tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL };
163 tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA };
164
165 tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV };
166 tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV };
167 tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV };
168
169 tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU };
170 tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU };
171 tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND };
172 tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR };
173 tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR };
174 tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR };
175 tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT };
176 tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU };
177
178 tagged J .it : return { opJ, it.target };
179 tagged JAL .it : return { opJAL, it.target };
180 tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR };
181 tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR };
182 tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset };
183 tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset };
184 tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset };
185 tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset };
186 tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset };
187 tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset };
188
189 tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 };
190 tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 };
191
192 endcase
193
194 endfunction
195
196 // Unpack Function
197
198 function Instr unpack( Bit#(32) instrBits );
199
200 let opcode = instrBits[ 31 : 26 ];
201 let rs = instrBits[ 25 : 21 ];
202 let rt = instrBits[ 20 : 16 ];
203 let rd = instrBits[ 15 : 11 ];
204 let shamt = instrBits[ 10 : 6 ];
205 let funct = instrBits[ 5 : 0 ];
206 let imm = instrBits[ 15 : 0 ];
207 let target = instrBits[ 25 : 0 ];
208
209 case ( opcode )
210
211 opLW : return LW { rbase:rs, rdst:rt, offset:imm };
212 opSW : return SW { rbase:rs, rsrc:rt, offset:imm };
213 opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm };
214 opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm };
215 opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm };
216 opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm };
217 opORI : return ORI { rsrc:rs, rdst:rt, imm:imm };
218 opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm };
219 opLUI : return LUI { rdst:rt, imm:imm };
220 opJ : return J { target:target };
221 opJAL : return JAL { target:target };
222 opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm };
223 opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm };
224 opBLEZ : return BLEZ { rsrc:rs, offset:imm };
225 opBGTZ : return BGTZ { rsrc:rs, offset:imm };
226
227 opFUNC :
228 case ( funct )
229 fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt };
230 fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt };
231 fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt };
232 fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs };
233 fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs };
234 fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs };
235 fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd };
236 fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd };
237 fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd };
238 fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd };
239 fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd };
240 fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd };
241 fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd };
242 fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd };
243 fcJR : return JR { rsrc:rs };
244 fcJALR : return JALR { rsrc:rs, rdst:rd };
245 default : return ILLEGAL;
246 endcase
247
248 opRT :
249 case ( rt )
250 rtBLTZ : return BLTZ { rsrc:rs, offset:imm };
251 rtBGEZ : return BGEZ { rsrc:rs, offset:imm };
252 default : return ILLEGAL;
253 endcase
254
255 opRS :
256 case ( rs )
257 rsMFC0 : return MFC0 { rdst:rt, cop0src:rd };
258 rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd };
259 default : return ILLEGAL;
260 endcase
261
262 default : return ILLEGAL;
263
264 endcase
265
266 endfunction
267
268 endinstance
269
270 //----------------------------------------------------------------------
271 // Trace
272 //----------------------------------------------------------------------
273
274 instance Traceable#(Instr);
275
276 function Action traceTiny( String loc, String ttag, Instr inst );
277 case ( inst ) matches
278
279 tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag );
280 tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag );
281
282 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag );
283 tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag );
284 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag );
285 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag );
286 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag );
287 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag );
288 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag );
289
290 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag );
291 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag );
292 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag );
293 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag );
294 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag );
295 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag );
296
297 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag );
298 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag );
299 tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag );
300 tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag );
301 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag );
302 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag );
303 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag );
304 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag );
305
306 tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag );
307 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag );
308 tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag );
309 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag );
310 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag );
311 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag );
312 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag );
313 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag );
314 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag );
315 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag );
316
317 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag );
318 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag );
319
320 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag );
321
322 endcase
323 endfunction
324
325 function Action traceFull( String loc, String ttag, Instr inst );
326 case ( inst ) matches
327
328 tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase );
329 tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase );
330
331 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
332 tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
333 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
334 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
335 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
336 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
337 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm );
338
339 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
340 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
341 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
342 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
343 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
344 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
345
346 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
347 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
348 tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
349 tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
350 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
351 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
352 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
353 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
354
355 tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target );
356 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target );
357 tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc );
358 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc );
359 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
360 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
361 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
362 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
363 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
364 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
365
366 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src );
367 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst );
368
369 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag );
370
371 endcase
372 endfunction
373
374 endinstance
375