Mercurial > pygar
comparison modules/bluespec/Pygar/lab4/oProcTypes.bsv @ 8:74716e9a81cc pygar svn.9
[svn r9] Pygar now has the proper directory structure to play nicely with awb. Also, the apm file for audio-core willcompile successfully.
author | rlm |
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date | Fri, 23 Apr 2010 02:32:05 -0400 |
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7:7393cd19371e | 8:74716e9a81cc |
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1 | |
2 import Trace::*; | |
3 | |
4 //---------------------------------------------------------------------- | |
5 // Other typedefs | |
6 //---------------------------------------------------------------------- | |
7 | |
8 typedef Bit#(32) Addr; | |
9 | |
10 //---------------------------------------------------------------------- | |
11 // Basic instruction type | |
12 //---------------------------------------------------------------------- | |
13 | |
14 typedef Bit#(5) Rindx; | |
15 typedef Bit#(16) Simm; | |
16 typedef Bit#(16) Zimm; | |
17 typedef Bit#(5) Shamt; | |
18 typedef Bit#(26) Target; | |
19 typedef Bit#(5) CP0indx; | |
20 | |
21 typedef union tagged | |
22 { | |
23 | |
24 struct { Rindx rbase; Rindx rdst; Simm offset; } LW; | |
25 struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; | |
26 | |
27 struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; | |
28 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; | |
29 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; | |
30 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; | |
31 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; | |
32 struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; | |
33 struct { Rindx rdst; Zimm imm; } LUI; | |
34 | |
35 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; | |
36 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; | |
37 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; | |
38 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; | |
39 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; | |
40 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; | |
41 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; | |
42 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; | |
43 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; | |
44 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; | |
45 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; | |
46 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; | |
47 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; | |
48 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; | |
49 | |
50 struct { Target target; } J; | |
51 struct { Target target; } JAL; | |
52 struct { Rindx rsrc; } JR; | |
53 struct { Rindx rsrc; Rindx rdst; } JALR; | |
54 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; | |
55 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; | |
56 struct { Rindx rsrc; Simm offset; } BLEZ; | |
57 struct { Rindx rsrc; Simm offset; } BGTZ; | |
58 struct { Rindx rsrc; Simm offset; } BLTZ; | |
59 struct { Rindx rsrc; Simm offset; } BGEZ; | |
60 | |
61 struct { Rindx rdst; CP0indx cop0src; } MFC0; | |
62 struct { Rindx rsrc; CP0indx cop0dst; } MTC0; | |
63 | |
64 void ILLEGAL; | |
65 | |
66 } | |
67 Instr deriving(Eq); | |
68 | |
69 //---------------------------------------------------------------------- | |
70 // Pack and Unpack | |
71 //---------------------------------------------------------------------- | |
72 | |
73 Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; | |
74 Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; | |
75 Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; | |
76 Bit#(6) fcSLLV = 6'b000100; | |
77 Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; | |
78 Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; | |
79 Bit#(6) fcADDU = 6'b100001; | |
80 Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; | |
81 Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; | |
82 Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; | |
83 Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; | |
84 Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; | |
85 Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; | |
86 Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; | |
87 | |
88 Bit#(6) opJ = 6'b000010; | |
89 Bit#(6) opJAL = 6'b000011; | |
90 Bit#(6) fcJR = 6'b001000; | |
91 Bit#(6) fcJALR = 6'b001001; | |
92 Bit#(6) opBEQ = 6'b000100; | |
93 Bit#(6) opBNE = 6'b000101; | |
94 Bit#(6) opBLEZ = 6'b000110; | |
95 Bit#(6) opBGTZ = 6'b000111; | |
96 Bit#(5) rtBLTZ = 5'b00000; | |
97 Bit#(5) rtBGEZ = 5'b00001; | |
98 | |
99 Bit#(5) rsMFC0 = 5'b00000; | |
100 Bit#(5) rsMTC0 = 5'b00100; | |
101 | |
102 instance Bits#(Instr,32); | |
103 | |
104 // Pack Function | |
105 | |
106 function Bit#(32) pack( Instr instr ); | |
107 | |
108 case ( instr ) matches | |
109 | |
110 tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; | |
111 tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; | |
112 | |
113 tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; | |
114 tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; | |
115 tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; | |
116 tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; | |
117 tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; | |
118 tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; | |
119 tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; | |
120 | |
121 tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; | |
122 tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; | |
123 tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; | |
124 | |
125 tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; | |
126 tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; | |
127 tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; | |
128 | |
129 tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; | |
130 tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; | |
131 tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; | |
132 tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; | |
133 tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; | |
134 tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; | |
135 tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; | |
136 tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; | |
137 | |
138 tagged J .it : return { opJ, it.target }; | |
139 tagged JAL .it : return { opJAL, it.target }; | |
140 tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; | |
141 tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; | |
142 tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; | |
143 tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; | |
144 tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; | |
145 tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; | |
146 tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; | |
147 tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; | |
148 | |
149 tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; | |
150 tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; | |
151 | |
152 endcase | |
153 | |
154 endfunction | |
155 | |
156 // Unpack Function | |
157 | |
158 function Instr unpack( Bit#(32) instrBits ); | |
159 | |
160 let opcode = instrBits[ 31 : 26 ]; | |
161 let rs = instrBits[ 25 : 21 ]; | |
162 let rt = instrBits[ 20 : 16 ]; | |
163 let rd = instrBits[ 15 : 11 ]; | |
164 let shamt = instrBits[ 10 : 6 ]; | |
165 let funct = instrBits[ 5 : 0 ]; | |
166 let imm = instrBits[ 15 : 0 ]; | |
167 let target = instrBits[ 25 : 0 ]; | |
168 | |
169 case ( opcode ) | |
170 | |
171 opLW : return LW { rbase:rs, rdst:rt, offset:imm }; | |
172 opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; | |
173 opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; | |
174 opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; | |
175 opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; | |
176 opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; | |
177 opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; | |
178 opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; | |
179 opLUI : return LUI { rdst:rt, imm:imm }; | |
180 opJ : return J { target:target }; | |
181 opJAL : return JAL { target:target }; | |
182 opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; | |
183 opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; | |
184 opBLEZ : return BLEZ { rsrc:rs, offset:imm }; | |
185 opBGTZ : return BGTZ { rsrc:rs, offset:imm }; | |
186 | |
187 opFUNC : | |
188 case ( funct ) | |
189 fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; | |
190 fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; | |
191 fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; | |
192 fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; | |
193 fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; | |
194 fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; | |
195 fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; | |
196 fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; | |
197 fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; | |
198 fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; | |
199 fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; | |
200 fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; | |
201 fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; | |
202 fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; | |
203 fcJR : return JR { rsrc:rs }; | |
204 fcJALR : return JALR { rsrc:rs, rdst:rd }; | |
205 default : return ILLEGAL; | |
206 endcase | |
207 | |
208 opRT : | |
209 case ( rt ) | |
210 rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; | |
211 rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; | |
212 default : return ILLEGAL; | |
213 endcase | |
214 | |
215 opRS : | |
216 case ( rs ) | |
217 rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; | |
218 rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; | |
219 default : return ILLEGAL; | |
220 endcase | |
221 | |
222 default : return ILLEGAL; | |
223 | |
224 endcase | |
225 | |
226 endfunction | |
227 | |
228 endinstance | |
229 | |
230 //---------------------------------------------------------------------- | |
231 // Trace | |
232 //---------------------------------------------------------------------- | |
233 | |
234 instance Traceable#(Instr); | |
235 | |
236 function Action traceTiny( String loc, String ttag, Instr inst ); | |
237 case ( inst ) matches | |
238 | |
239 tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); | |
240 tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); | |
241 | |
242 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); | |
243 tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); | |
244 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); | |
245 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); | |
246 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); | |
247 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); | |
248 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); | |
249 | |
250 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); | |
251 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); | |
252 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); | |
253 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); | |
254 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); | |
255 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); | |
256 | |
257 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); | |
258 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); | |
259 tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); | |
260 tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); | |
261 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); | |
262 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); | |
263 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); | |
264 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); | |
265 | |
266 tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); | |
267 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); | |
268 tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); | |
269 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); | |
270 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); | |
271 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); | |
272 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); | |
273 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); | |
274 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); | |
275 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); | |
276 | |
277 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); | |
278 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); | |
279 | |
280 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); | |
281 | |
282 endcase | |
283 endfunction | |
284 | |
285 function Action traceFull( String loc, String ttag, Instr inst ); | |
286 case ( inst ) matches | |
287 | |
288 tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); | |
289 tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); | |
290 | |
291 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); | |
292 tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); | |
293 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); | |
294 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); | |
295 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); | |
296 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); | |
297 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); | |
298 | |
299 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); | |
300 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); | |
301 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); | |
302 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); | |
303 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); | |
304 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); | |
305 | |
306 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); | |
307 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); | |
308 tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); | |
309 tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); | |
310 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); | |
311 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); | |
312 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); | |
313 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); | |
314 | |
315 tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); | |
316 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); | |
317 tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); | |
318 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); | |
319 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); | |
320 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); | |
321 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); | |
322 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); | |
323 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); | |
324 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); | |
325 | |
326 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); | |
327 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); | |
328 | |
329 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); | |
330 | |
331 endcase | |
332 endfunction | |
333 | |
334 endinstance | |
335 |