Mercurial > pygar
diff modules/bluespec/Pygar/lab4/oProcTypes.bsv @ 8:74716e9a81cc pygar svn.9
[svn r9] Pygar now has the proper directory structure to play nicely with awb. Also, the apm file for audio-core willcompile successfully.
author | rlm |
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date | Fri, 23 Apr 2010 02:32:05 -0400 |
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1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/modules/bluespec/Pygar/lab4/oProcTypes.bsv Fri Apr 23 02:32:05 2010 -0400 1.3 @@ -0,0 +1,335 @@ 1.4 + 1.5 +import Trace::*; 1.6 + 1.7 +//---------------------------------------------------------------------- 1.8 +// Other typedefs 1.9 +//---------------------------------------------------------------------- 1.10 + 1.11 +typedef Bit#(32) Addr; 1.12 + 1.13 +//---------------------------------------------------------------------- 1.14 +// Basic instruction type 1.15 +//---------------------------------------------------------------------- 1.16 + 1.17 +typedef Bit#(5) Rindx; 1.18 +typedef Bit#(16) Simm; 1.19 +typedef Bit#(16) Zimm; 1.20 +typedef Bit#(5) Shamt; 1.21 +typedef Bit#(26) Target; 1.22 +typedef Bit#(5) CP0indx; 1.23 + 1.24 +typedef union tagged 1.25 +{ 1.26 + 1.27 + struct { Rindx rbase; Rindx rdst; Simm offset; } LW; 1.28 + struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; 1.29 + 1.30 + struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; 1.31 + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; 1.32 + struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; 1.33 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; 1.34 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; 1.35 + struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; 1.36 + struct { Rindx rdst; Zimm imm; } LUI; 1.37 + 1.38 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; 1.39 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; 1.40 + struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; 1.41 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; 1.42 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; 1.43 + struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; 1.44 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; 1.45 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; 1.46 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; 1.47 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; 1.48 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; 1.49 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; 1.50 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; 1.51 + struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; 1.52 + 1.53 + struct { Target target; } J; 1.54 + struct { Target target; } JAL; 1.55 + struct { Rindx rsrc; } JR; 1.56 + struct { Rindx rsrc; Rindx rdst; } JALR; 1.57 + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; 1.58 + struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; 1.59 + struct { Rindx rsrc; Simm offset; } BLEZ; 1.60 + struct { Rindx rsrc; Simm offset; } BGTZ; 1.61 + struct { Rindx rsrc; Simm offset; } BLTZ; 1.62 + struct { Rindx rsrc; Simm offset; } BGEZ; 1.63 + 1.64 + struct { Rindx rdst; CP0indx cop0src; } MFC0; 1.65 + struct { Rindx rsrc; CP0indx cop0dst; } MTC0; 1.66 + 1.67 + void ILLEGAL; 1.68 + 1.69 +} 1.70 +Instr deriving(Eq); 1.71 + 1.72 +//---------------------------------------------------------------------- 1.73 +// Pack and Unpack 1.74 +//---------------------------------------------------------------------- 1.75 + 1.76 +Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; 1.77 +Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; 1.78 +Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; 1.79 + Bit#(6) fcSLLV = 6'b000100; 1.80 +Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; 1.81 +Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; 1.82 + Bit#(6) fcADDU = 6'b100001; 1.83 +Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; 1.84 +Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; 1.85 +Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; 1.86 +Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; 1.87 +Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; 1.88 +Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; 1.89 +Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; 1.90 + 1.91 +Bit#(6) opJ = 6'b000010; 1.92 +Bit#(6) opJAL = 6'b000011; 1.93 +Bit#(6) fcJR = 6'b001000; 1.94 +Bit#(6) fcJALR = 6'b001001; 1.95 +Bit#(6) opBEQ = 6'b000100; 1.96 +Bit#(6) opBNE = 6'b000101; 1.97 +Bit#(6) opBLEZ = 6'b000110; 1.98 +Bit#(6) opBGTZ = 6'b000111; 1.99 +Bit#(5) rtBLTZ = 5'b00000; 1.100 +Bit#(5) rtBGEZ = 5'b00001; 1.101 + 1.102 +Bit#(5) rsMFC0 = 5'b00000; 1.103 +Bit#(5) rsMTC0 = 5'b00100; 1.104 + 1.105 +instance Bits#(Instr,32); 1.106 + 1.107 + // Pack Function 1.108 + 1.109 + function Bit#(32) pack( Instr instr ); 1.110 + 1.111 + case ( instr ) matches 1.112 + 1.113 + tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; 1.114 + tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; 1.115 + 1.116 + tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; 1.117 + tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; 1.118 + tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; 1.119 + tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; 1.120 + tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; 1.121 + tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; 1.122 + tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; 1.123 + 1.124 + tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; 1.125 + tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; 1.126 + tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; 1.127 + 1.128 + tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; 1.129 + tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; 1.130 + tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; 1.131 + 1.132 + tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; 1.133 + tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; 1.134 + tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; 1.135 + tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; 1.136 + tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; 1.137 + tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; 1.138 + tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; 1.139 + tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; 1.140 + 1.141 + tagged J .it : return { opJ, it.target }; 1.142 + tagged JAL .it : return { opJAL, it.target }; 1.143 + tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; 1.144 + tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; 1.145 + tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; 1.146 + tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; 1.147 + tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; 1.148 + tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; 1.149 + tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; 1.150 + tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; 1.151 + 1.152 + tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; 1.153 + tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; 1.154 + 1.155 + endcase 1.156 + 1.157 + endfunction 1.158 + 1.159 + // Unpack Function 1.160 + 1.161 + function Instr unpack( Bit#(32) instrBits ); 1.162 + 1.163 + let opcode = instrBits[ 31 : 26 ]; 1.164 + let rs = instrBits[ 25 : 21 ]; 1.165 + let rt = instrBits[ 20 : 16 ]; 1.166 + let rd = instrBits[ 15 : 11 ]; 1.167 + let shamt = instrBits[ 10 : 6 ]; 1.168 + let funct = instrBits[ 5 : 0 ]; 1.169 + let imm = instrBits[ 15 : 0 ]; 1.170 + let target = instrBits[ 25 : 0 ]; 1.171 + 1.172 + case ( opcode ) 1.173 + 1.174 + opLW : return LW { rbase:rs, rdst:rt, offset:imm }; 1.175 + opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; 1.176 + opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; 1.177 + opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; 1.178 + opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; 1.179 + opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; 1.180 + opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; 1.181 + opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; 1.182 + opLUI : return LUI { rdst:rt, imm:imm }; 1.183 + opJ : return J { target:target }; 1.184 + opJAL : return JAL { target:target }; 1.185 + opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; 1.186 + opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; 1.187 + opBLEZ : return BLEZ { rsrc:rs, offset:imm }; 1.188 + opBGTZ : return BGTZ { rsrc:rs, offset:imm }; 1.189 + 1.190 + opFUNC : 1.191 + case ( funct ) 1.192 + fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; 1.193 + fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; 1.194 + fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; 1.195 + fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; 1.196 + fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; 1.197 + fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; 1.198 + fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.199 + fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.200 + fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.201 + fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.202 + fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.203 + fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.204 + fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.205 + fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; 1.206 + fcJR : return JR { rsrc:rs }; 1.207 + fcJALR : return JALR { rsrc:rs, rdst:rd }; 1.208 + default : return ILLEGAL; 1.209 + endcase 1.210 + 1.211 + opRT : 1.212 + case ( rt ) 1.213 + rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; 1.214 + rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; 1.215 + default : return ILLEGAL; 1.216 + endcase 1.217 + 1.218 + opRS : 1.219 + case ( rs ) 1.220 + rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; 1.221 + rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; 1.222 + default : return ILLEGAL; 1.223 + endcase 1.224 + 1.225 + default : return ILLEGAL; 1.226 + 1.227 + endcase 1.228 + 1.229 + endfunction 1.230 + 1.231 +endinstance 1.232 + 1.233 +//---------------------------------------------------------------------- 1.234 +// Trace 1.235 +//---------------------------------------------------------------------- 1.236 + 1.237 +instance Traceable#(Instr); 1.238 + 1.239 + function Action traceTiny( String loc, String ttag, Instr inst ); 1.240 + case ( inst ) matches 1.241 + 1.242 + tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); 1.243 + tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); 1.244 + 1.245 + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); 1.246 + tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); 1.247 + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); 1.248 + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); 1.249 + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); 1.250 + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); 1.251 + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); 1.252 + 1.253 + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); 1.254 + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); 1.255 + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); 1.256 + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); 1.257 + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); 1.258 + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); 1.259 + 1.260 + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); 1.261 + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); 1.262 + tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); 1.263 + tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); 1.264 + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); 1.265 + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); 1.266 + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); 1.267 + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); 1.268 + 1.269 + tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); 1.270 + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); 1.271 + tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); 1.272 + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); 1.273 + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); 1.274 + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); 1.275 + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); 1.276 + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); 1.277 + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); 1.278 + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); 1.279 + 1.280 + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); 1.281 + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); 1.282 + 1.283 + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); 1.284 + 1.285 + endcase 1.286 + endfunction 1.287 + 1.288 + function Action traceFull( String loc, String ttag, Instr inst ); 1.289 + case ( inst ) matches 1.290 + 1.291 + tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); 1.292 + tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); 1.293 + 1.294 + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.295 + tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.296 + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.297 + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.298 + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.299 + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 1.300 + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); 1.301 + 1.302 + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 1.303 + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 1.304 + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 1.305 + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 1.306 + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 1.307 + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 1.308 + 1.309 + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.310 + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.311 + tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.312 + tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.313 + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.314 + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.315 + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.316 + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 1.317 + 1.318 + tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); 1.319 + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); 1.320 + tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); 1.321 + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); 1.322 + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 1.323 + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 1.324 + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 1.325 + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 1.326 + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 1.327 + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 1.328 + 1.329 + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); 1.330 + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); 1.331 + 1.332 + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); 1.333 + 1.334 + endcase 1.335 + endfunction 1.336 + 1.337 +endinstance 1.338 +