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comparison modules/bluespec/Pygar/lab4/InstCacheBlocking.bsv @ 49:61f6267cb3db pygar svn.50

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[svn r50] removed problematic stats stuff
author rlm
date Wed, 05 May 2010 14:40:48 -0400
parents 3958de09a7c1
children 9fe5ed4af92d
comparison
equal deleted inserted replaced
48:a139cc07b773 49:61f6267cb3db
130 130
131 // Statistics state 131 // Statistics state
132 132
133 Reg#(Bool) statsEn <- mkReg(False); 133 Reg#(Bool) statsEn <- mkReg(False);
134 134
135 STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES); 135 //rlm:
136 STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES); 136 //STAT num_accesses <- mkStatCounter(`STATS_INST_CACHE_NUM_ACCESSES);
137 STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS); 137 //STAT num_misses <- mkStatCounter(`STATS_INST_CACHE_NUM_MISSES);
138 //STAT num_evictions <- mkStatCounter(`STATS_INST_CACHE_NUM_EVICTIONS);
138 139
139 //----------------------------------------------------------- 140 //-----------------------------------------------------------
140 // Name some wires 141 // Name some wires
141 142
142 let req = reqQ.first(); 143 let req = reqQ.first();
160 // Cache access rule 161 // Cache access rule
161 162
162 rule access ( (stage == Access) && respQ.notFull() ); 163 rule access ( (stage == Access) && respQ.notFull() );
163 164
164 // Statistics 165 // Statistics
165 166 //rlm:
166 if ( statsEn ) 167 // if ( statsEn )
167 num_accesses.incr(); 168 // num_accesses.incr();
168 169
169 // Check tag and valid bit to see if this is a hit or a miss 170 // Check tag and valid bit to see if this is a hit or a miss
170 171
171 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex); 172 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
172 173
193 // never dirty we can always immediately issue a refill request 194 // never dirty we can always immediately issue a refill request
194 195
195 else 196 else
196 begin 197 begin
197 traceTiny("mkInstCacheBlocking", "hitMiss","m"); 198 traceTiny("mkInstCacheBlocking", "hitMiss","m");
198 if ( statsEn ) 199 //rlm:
199 num_misses.incr(); 200 //if ( statsEn )
200 if ( statsEn ) 201 //num_misses.incr();
201 if ( isJust(cacheLineTag) ) 202 //if ( statsEn )
202 num_evictions.incr(); 203 //if ( isJust(cacheLineTag) )
204 //num_evictions.incr();
203 205
204 MainMemReq rfReq 206 MainMemReq rfReq
205 = LoadReq { tag : 0, 207 = LoadReq { tag : 0,
206 addr : reqCacheLineAddr }; 208 addr : reqCacheLineAddr };
207 209