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comparison modules/bluespec/Pygar/core/audioCorePipeline.bsv @ 43:4d87fa55a776 pygar svn.44

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[svn r44] processor largely working and mixer in good status
author punk
date Wed, 05 May 2010 12:28:07 -0400
parents ced2ebd41347
children 97d1959f7c5c
comparison
equal deleted inserted replaced
42:ced2ebd41347 43:4d87fa55a776
35 35
36 //Local includes 36 //Local includes
37 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface 37 `include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface
38 `include "asim/provides/path_types.bsh" 38 `include "asim/provides/path_types.bsh"
39 `include "asim/provides/core.bsh" 39 `include "asim/provides/core.bsh"
40 //`include "asim/provides/mixer.bsh" 40 `include "asim/provides/mixer.bsh"
41 `include "asim/provides/processor_library.bsh" 41 `include "asim/provides/processor_library.bsh"
42 `include "asim/provides/fpga_components.bsh" 42 `include "asim/provides/fpga_components.bsh"
43 `include "asim/provides/scratchpad_memory.bsh" 43 `include "asim/provides/scratchpad_memory.bsh"
44 `include "asim/provides/mem_services.bsh" 44 `include "asim/provides/mem_services.bsh"
45 `include "asim/dict/VDEV_SCRATCH.bsh" 45 `include "asim/dict/VDEV_SCRATCH.bsh"
77 77
78 rule sendMemReq; 78 rule sendMemReq;
79 let coreReq <- core.mmem_client.request.get; 79 let coreReq <- core.mmem_client.request.get;
80 case (coreReq) matches 80 case (coreReq) matches
81 tagged LoadReq .load: begin 81 tagged LoadReq .load: begin
82 $display("PIPE Load Addr Req %x", load.addr); 82 // $display("PIPE Load Addr Req %h", load.addr);
83 //Allocate ROB space 83 //Allocate ROB space
84 memory.readReq(truncate(load.addr>>2)); 84 memory.readReq(truncate(load.addr>>2));
85 tags.enq(load.tag); 85 tags.enq(load.tag);
86 end 86 end
87 tagged StoreReq .store: begin 87 tagged StoreReq .store: begin
88 $display("PIPE Write Addr Req %x", store.addr); 88 // $display("PIPE Write Addr Req %h", store.addr);
89 memory.write(truncate(store.addr>>2),store.data); 89 memory.write(truncate(store.addr>>2),store.data);
90 end 90 end
91 endcase 91 endcase
92 endrule 92 endrule
93 93
94 rule receiveMemResp; 94 rule receiveMemResp;
95 let memResp <- memory.readRsp(); 95 let memResp <- memory.readRsp();
96 tags.deq; 96 tags.deq;
97 core.mmem_client.response.put(tagged LoadResp {data:memResp, 97 core.mmem_client.response.put(tagged LoadResp {data:memResp,
98 tag: tags.first}); 98 tag: tags.first});
99 $display("PIPE Receive MemReq %x", memResp); 99 // $display("PIPE Receive MemReq %x", memResp);
100 endrule 100 endrule
101 101
102 rule feedOutput; 102 rule feedOutput;
103 let pipelineData <- core.sampleOutput.get(); 103 let pipelineData <- core.sampleOutput.get();
104 AudioProcessorControl endOfFileTag = EndOfFile; 104 AudioProcessorControl endOfFileTag = EndOfFile;
129 $display("rlm: %x", test); 129 $display("rlm: %x", test);
130 130
131 131
132 if(ctrl == EndOfFile) 132 if(ctrl == EndOfFile)
133 begin 133 begin
134 $display("lsp: PROCESSOR received EOF "); 134 $display("lsp: PIPE received EOF ");
135 core.sampleInput.put(tagged EndOfFile); 135 core.sampleInput.put(tagged EndOfFile);
136 end 136 end
137 else 137 else
138 begin 138 begin
139 $display("lsp: PROCESSOR received Data "); 139 // $display("lsp: PIPE received Data ");
140 core.sampleInput.put(tagged Sample unpack(truncate(command.sample))); 140 core.sampleInput.put(tagged Sample unpack(truncate(command.sample)));
141 end 141 end
142 endrule 142 endrule
143 endmodule 143 endmodule