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annotate modules/bluespec/Pygar/core/#Processor.bsv# @ 65:cf8bb3038cbd pygar svn.66

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[svn r66] sim passes
author punk
date Tue, 11 May 2010 09:05:22 -0400
parents 2b18894f75e2
children
rev   line source
punk@26 1 /// The MIT License
punk@26 2
punk@26 3 // Copyright (c) 2009 Massachusetts Institute of Technology
punk@26 4
punk@26 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
punk@26 6 // of this software and associated documentation files (the "Software"), to deal
punk@26 7 // in the Software without restriction, including without limitation the rights
punk@26 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
punk@26 9 // copies of the Software, and to permit persons to whom the Software is
punk@26 10 // furnished to do so, subject to the following conditions:
punk@26 11
punk@26 12 // The above copyright notice and this permission notice shall be included in
punk@26 13 // all copies or substantial portions of the Software.
punk@26 14
punk@26 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
punk@26 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
punk@26 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
punk@26 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
punk@26 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
punk@26 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
punk@26 21 // THE SOFTWARE.
punk@26 22
punk@26 23
punk@26 24 import Connectable::*;
punk@26 25 import GetPut::*;
punk@26 26 import ClientServer::*;
punk@26 27 import RegFile::*;
punk@26 28
punk@26 29 import FIFO::*;
punk@26 30 import FIFOF::*;
punk@26 31 import SFIFO::*;
punk@26 32 import RWire::*;
punk@36 33
punk@26 34 import Trace::*;
punk@26 35 import BFIFO::*;
punk@36 36 import MemTypes::*;
punk@26 37 import ProcTypes::*;
punk@26 38 import BRegFile::*;
punk@26 39 import BranchPred::*;
punk@26 40 //import PathTypes::*; This is only there to force the debugging
punk@26 41
punk@26 42 //AWB includes
punk@26 43 `include "asim/provides/low_level_platform_interface.bsh"
punk@26 44 `include "asim/provides/soft_connections.bsh"
punk@26 45 `include "asim/provides/common_services.bsh"
punk@26 46
punk@26 47 // Local includes
punk@26 48 //`include "asim/provides/processor_library.bsh" (included above directly)
punk@36 49
punk@26 50 `include "asim/provides/common_services.bsh"
punk@26 51 `include "asim/dict/STATS_PROCESSOR.bsh"
punk@26 52 `include "asim/provides/processor_library.bsh"
punk@26 53
punk@26 54 // Local includes. Look for the correspondingly named .awb files
punk@26 55 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@26 56 // to find the actual Bluespec files which are used to generate
punk@26 57 // these includes. These files are specific to this audio processing
punk@26 58 // pipeline
punk@26 59
punk@26 60 `include "asim/provides/audio_pipe_types.bsh"
punk@26 61
punk@26 62 //interface CPUToHost;
punk@26 63 // method Bit#(32) cpuToHost(int req);
punk@26 64 //endinterface
punk@26 65
punk@26 66 interface Proc;
punk@26 67
punk@26 68 // Interface from processor to caches
punk@26 69 interface Client#(DataReq,DataResp) dmem_client;
punk@26 70 interface Client#(InstReq,InstResp) imem_client;
punk@26 71
punk@26 72 // Interface for enabling/disabling statistics on the rest of the core
punk@26 73 interface Get#(Bool) statsEn_get;
punk@26 74
punk@26 75 // // Interface to host
punk@26 76 // interface CPUToHost tohost;
punk@26 77
punk@26 78 // Interface to Audio Pipeline
punk@26 79 interface Get#(AudioProcessorUnit) sampleOutput;
punk@36 80 interface Put#(AudioProcessorUnit) sampleInput;
punk@26 81
punk@26 82 endinterface
punk@26 83
punk@26 84 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
punk@26 85
punk@26 86 //-----------------------------------------------------------
punk@26 87 // Register file module
punk@26 88 //-----------------------------------------------------------
punk@26 89
punk@26 90 interface BRFile;
punk@26 91 method Action wr( Rindx rindx, Bit#(32) data );
punk@26 92 method Bit#(32) rd1( Rindx rindx );
punk@26 93 method Bit#(32) rd2( Rindx rindx );
punk@26 94 endinterface
punk@26 95
punk@26 96 module mkBRFile( BRFile );
punk@26 97
punk@26 98 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
punk@26 99
punk@26 100 method Action wr( Rindx rindx, Bit#(32) data );
punk@26 101 rfile.upd( rindx, data );
punk@26 102 endmethod
punk@26 103
punk@26 104 method Bit#(32) rd1( Rindx rindx );
punk@26 105 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
punk@26 106 endmethod
punk@26 107
punk@26 108 method Bit#(32) rd2( Rindx rindx );
punk@26 109 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
punk@26 110 endmethod
punk@26 111
punk@26 112 endmodule
punk@26 113
punk@26 114 //-----------------------------------------------------------
punk@26 115 // Helper functions
punk@26 116 //-----------------------------------------------------------
punk@26 117
punk@26 118 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
punk@26 119 return zeroExtend( pack( signedLT(val1,val2) ) );
punk@26 120 endfunction
punk@26 121
punk@26 122 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
punk@26 123 return zeroExtend( pack( val1 < val2 ) );
punk@26 124 endfunction
punk@26 125
punk@26 126 function Bit#(32) rshft( Bit#(32) val );
punk@26 127 return zeroExtend(val[4:0]);
punk@26 128 endfunction
punk@26 129
punk@26 130
punk@26 131 //-----------------------------------------------------------
punk@26 132 // Find funct for wbQ
punk@26 133 //-----------------------------------------------------------
punk@26 134 function Bool findwbf(Rindx fVal, WBResult cmpVal);
punk@26 135 case (cmpVal) matches
punk@26 136 tagged WB_ALU {data:.res, dest:.rd} :
punk@26 137 return (fVal == rd);
punk@26 138 tagged WB_Load .rd :
punk@26 139 return (fVal == rd);
punk@26 140 tagged WB_Store .st :
punk@26 141 return False;
punk@26 142 tagged WB_Host .x :
punk@26 143 return False;
punk@26 144 endcase
punk@26 145 endfunction
punk@26 146
punk@26 147
punk@26 148 //-----------------------------------------------------------
punk@26 149 // Stall funct for wbQ
punk@26 150 //-----------------------------------------------------------
punk@26 151 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
punk@26 152 case (inst) matches
punk@26 153 // -- Memory Ops ------------------------------------------------
punk@26 154 tagged LW .it :
punk@26 155 return f.find(it.rbase);
punk@26 156 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
punk@26 157 return (f.find(addr) || f.find2(dreg));
punk@26 158
punk@26 159 // -- Simple Ops ------------------------------------------------
punk@26 160 tagged ADDIU .it : return f.find(it.rsrc);
punk@26 161 tagged SLTI .it : return f.find(it.rsrc);
punk@26 162 tagged SLTIU .it : return f.find(it.rsrc);
punk@26 163 tagged ANDI .it : return f.find(it.rsrc);
punk@26 164 tagged ORI .it : return f.find(it.rsrc);
punk@26 165 tagged XORI .it : return f.find(it.rsrc);
punk@26 166
punk@26 167 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
punk@26 168 tagged SLL .it : return f.find(it.rsrc);
punk@26 169 tagged SRL .it : return f.find(it.rsrc);
punk@26 170 tagged SRA .it : return f.find(it.rsrc);
punk@26 171 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
punk@26 172 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
punk@26 173 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
punk@26 174 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 175 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 176 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 177 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 178 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 179 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 180 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 181 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 182
punk@26 183
punk@26 184 // -- Branches --------------------------------------------------
punk@26 185
punk@26 186 tagged BLEZ .it : return (f.find(it.rsrc));
punk@26 187 tagged BGTZ .it : return (f.find(it.rsrc));
punk@26 188 tagged BLTZ .it : return (f.find(it.rsrc));
punk@26 189 tagged BGEZ .it : return (f.find(it.rsrc));
punk@26 190 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 191 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
punk@26 192
punk@26 193 // -- Jumps -----------------------------------------------------
punk@26 194
punk@26 195 tagged J .it : return False;
punk@26 196 tagged JR .it : return f.find(it.rsrc);
punk@26 197 tagged JALR .it : return f.find(it.rsrc);
punk@26 198 tagged JAL .it : return False;
punk@26 199
punk@26 200 // -- Cop0 ------------------------------------------------------
punk@26 201
punk@26 202 tagged MTC0 .it : return f.find(it.rsrc);
punk@26 203 tagged MFC0 .it : return False;
punk@26 204
punk@26 205 // -- Illegal ---------------------------------------------------
punk@26 206
punk@26 207 default : return False;
punk@26 208
punk@26 209 endcase
punk@26 210 endfunction
punk@26 211 //-----------------------------------------------------------
punk@26 212 // Reference processor
punk@26 213 //-----------------------------------------------------------
punk@26 214
punk@26 215
punk@26 216 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
punk@26 217 //(* synthesize *)
punk@26 218
punk@26 219 module [CONNECTED_MODULE] mkProc( Proc );
punk@26 220
punk@26 221 //-----------------------------------------------------------
punk@26 222 // State
punk@26 223
punk@26 224 // Standard processor state
punk@26 225
punk@26 226 Reg#(Addr) pc <- mkReg(32'h00001000);
punk@26 227 Reg#(Epoch) epoch <- mkReg(0);
punk@26 228 Reg#(Stage) stage <- mkReg(PCgen);
punk@26 229 BRFile rf <- mkBRFile;
punk@26 230
punk@26 231 // Branch Prediction
punk@26 232 BranchPred bp <- mkBranchPred();
punk@26 233 FIFO#(PCStat) execpc <- mkLFIFO();
punk@26 234
punk@26 235 // Pipelines
punk@26 236 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
punk@26 237 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
punk@26 238
punk@36 239 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
punk@26 240 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
punk@26 241 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
punk@26 242 Reg#(Bool) cp0_statsEn <- mkReg(False);
punk@36 243 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
punk@36 244 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
punk@36 245
punk@26 246 // Memory request/response state
punk@26 247
punk@26 248 FIFO#(InstReq) instReqQ <- mkBFIFO1();
punk@26 249 FIFO#(InstResp) instRespQ <- mkFIFO();
punk@26 250
punk@26 251 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
punk@26 252 FIFO#(DataResp) dataRespQ <- mkFIFO();
punk@26 253
punk@26 254 // Audio I/O
punk@50 255 FIFO#(AudioProcessorUnit) inAudioFifo <- mkSizedFIFO(512);
punk@26 256 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
punk@26 257
punk@26 258
punk@26 259 // Statistics state (2010)
punk@36 260 // Reg#(Stat) num_cycles <- mkReg(0);
punk@36 261 // Reg#(Stat) num_inst <- mkReg(0);
punk@26 262
punk@26 263 //Or:
punk@26 264 // Statistics state
punk@26 265 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
punk@26 266 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
punk@26 267
punk@26 268 //-----------------------------------------------------------
punk@26 269 // Rules
punk@26 270
punk@26 271 (* descending_urgency = "exec, pcgen" *)
punk@26 272 rule pcgen; //( stage == PCgen );
punk@26 273 let pc_plus4 = pc + 4;
punk@26 274
punk@26 275 traceTiny("mkProc", "pc",pc);
punk@26 276 traceTiny("mkProc", "pcgen","P");
punk@26 277 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
punk@26 278
punk@26 279 let next_pc = bp.get(pc);
punk@26 280 if (next_pc matches tagged Valid .npc)
punk@26 281 begin
punk@26 282 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
punk@26 283 pc <= npc;
punk@26 284 end
punk@26 285 else
punk@26 286 begin
punk@26 287 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
punk@26 288 pc <= pc_plus4;
punk@26 289 end
punk@26 290
punk@26 291 endrule
punk@26 292
punk@26 293 rule discard (instRespQ.first() matches tagged LoadResp .ld
punk@26 294 &&& ld.tag != epoch);
punk@26 295 traceTiny("mkProc", "stage", "D");
punk@26 296 instRespQ.deq();
punk@26 297 endrule
punk@26 298
punk@26 299 (* conflict_free = "exec, writeback" *)
punk@26 300 rule exec (instRespQ.first() matches tagged LoadResp.ld
punk@26 301 &&& (ld.tag == epoch)
punk@26 302 &&& unpack(ld.data) matches .inst
punk@26 303 &&& !stall(inst, wbQ));
punk@26 304
punk@26 305 // Some abbreviations
punk@26 306 let sext = signExtend;
punk@26 307 let zext = zeroExtend;
punk@26 308 let sra = signedShiftRight;
punk@26 309
punk@26 310 // Get the instruction
punk@26 311
punk@26 312 instRespQ.deq();
punk@26 313 Instr inst
punk@26 314 = case ( instRespQ.first() ) matches
punk@26 315 tagged LoadResp .ld : return unpack(ld.data);
punk@26 316 tagged StoreResp .st : return ?;
punk@26 317 endcase;
punk@26 318
punk@26 319 // Get the PC info
punk@26 320 let instrpc = pcQ.first().qpc;
punk@26 321 let pc_plus4 = instrpc + 4;
punk@26 322
punk@26 323 Bool branchTaken = False;
punk@26 324 Addr newPC = pc_plus4;
punk@26 325
punk@26 326 // Tracing
punk@26 327 traceTiny("mkProc", "exec","X");
punk@26 328 traceTiny("mkProc", "exInstTiny",inst);
punk@26 329 traceFull("mkProc", "exInstFull",inst);
punk@26 330
punk@26 331 case ( inst ) matches
punk@26 332
punk@26 333 // -- Memory Ops ------------------------------------------------
punk@26 334
punk@26 335 tagged LW .it :
punk@26 336 begin
punk@26 337 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
punk@26 338 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
punk@26 339 wbQ.enq(tagged WB_Load it.rdst);
punk@26 340 end
punk@26 341
punk@26 342 tagged SW .it :
punk@26 343 begin
punk@26 344 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
punk@26 345 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
punk@26 346 wbQ.enq(tagged WB_Store);
punk@26 347 end
punk@26 348
punk@26 349 // -- Simple Ops ------------------------------------------------
punk@26 350
punk@26 351 tagged ADDIU .it :
punk@26 352 begin
punk@26 353 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
punk@26 354 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
punk@26 355 end
punk@26 356 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
punk@26 357 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
punk@26 358 tagged ANDI .it :
punk@26 359 begin
punk@26 360 Bit#(32) zext_it_imm = zext(it.imm);
punk@26 361 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
punk@26 362 end
punk@26 363 tagged ORI .it :
punk@26 364 begin
punk@26 365 Bit#(32) zext_it_imm = zext(it.imm);
punk@26 366 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
punk@26 367 end
punk@26 368 tagged XORI .it :
punk@26 369 begin
punk@26 370 Bit#(32) zext_it_imm = zext(it.imm);
punk@26 371 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
punk@26 372 end
punk@26 373 tagged LUI .it :
punk@26 374 begin
punk@26 375 Bit#(32) zext_it_imm = zext(it.imm);
punk@26 376 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
punk@26 377 end
punk@26 378
punk@26 379 tagged SLL .it :
punk@26 380 begin
punk@26 381 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@26 382 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
punk@26 383 end
punk@26 384 tagged SRL .it :
punk@26 385 begin
punk@26 386 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@26 387 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
punk@26 388 end
punk@26 389 tagged SRA .it :
punk@26 390 begin
punk@26 391 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@26 392 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
punk@26 393 end
punk@26 394 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
punk@26 395 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
punk@26 396 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
punk@26 397 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
punk@26 398 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
punk@26 399 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
punk@26 400 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
punk@26 401 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
punk@26 402 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
punk@26 403 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
punk@26 404 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
punk@26 405
punk@26 406 // -- Branches --------------------------------------------------
punk@26 407
punk@26 408 tagged BLEZ .it :
punk@26 409 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
punk@26 410 begin
punk@26 411 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 412 branchTaken = True;
punk@26 413 end
punk@26 414
punk@26 415 tagged BGTZ .it :
punk@26 416 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
punk@26 417 begin
punk@26 418 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 419 branchTaken = True;
punk@26 420 end
punk@26 421
punk@26 422 tagged BLTZ .it :
punk@26 423 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
punk@26 424 begin
punk@26 425 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 426 branchTaken = True;
punk@26 427 end
punk@26 428
punk@26 429 tagged BGEZ .it :
punk@26 430 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
punk@26 431 begin
punk@26 432 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 433 branchTaken = True;
punk@26 434 end
punk@26 435
punk@26 436 tagged BEQ .it :
punk@26 437 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
punk@26 438 begin
punk@26 439 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 440 branchTaken = True;
punk@26 441 end
punk@26 442
punk@26 443 tagged BNE .it :
punk@26 444 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
punk@26 445 begin
punk@26 446 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@26 447 branchTaken = True;
punk@26 448 end
punk@26 449
punk@26 450 // -- Jumps -----------------------------------------------------
punk@26 451
punk@26 452 tagged J .it :
punk@26 453 begin
punk@26 454 newPC = { pc_plus4[31:28], it.target, 2'b0 };
punk@26 455 branchTaken = True;
punk@26 456 end
punk@26 457
punk@26 458 tagged JR .it :
punk@50 459 begin
punk@26 460 newPC = rf.rd1(it.rsrc);
punk@26 461 branchTaken = True;
punk@26 462 end
punk@26 463
punk@26 464 tagged JAL .it :
punk@26 465 begin
punk@26 466 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
punk@26 467 newPC = { pc_plus4[31:28], it.target, 2'b0 };
punk@26 468 branchTaken = True;
punk@26 469 end
punk@26 470
punk@26 471 tagged JALR .it :
punk@26 472 begin
punk@26 473 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
punk@26 474 newPC = rf.rd1(it.rsrc);
punk@26 475 branchTaken = True;
punk@26 476 end
punk@26 477
punk@26 478 // -- Cop0 ------------------------------------------------------
punk@26 479
punk@36 480 tagged MTC0 .it : //Recieve things from host computer
punk@26 481 begin
punk@50 482 // $display( " PROCESSOR MTC0 call\n");
punk@26 483 case ( it.cop0dst )
punk@26 484 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
punk@26 485 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
punk@36 486 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
punk@36 487 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32
punk@26 488 default :
punk@26 489 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
punk@26 490 endcase
punk@26 491 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
punk@26 492 end
punk@26 493
punk@26 494 //this is host stuff?
punk@36 495 tagged MFC0 .it : //Things out
punk@26 496 begin
punk@26 497 case ( it.cop0src )
punk@26 498 // not actually an ALU instruction but don't have the format otherwise
punk@26 499 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
punk@26 500 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
punk@26 501 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
punk@36 502 5'd25 : begin
punk@50 503 / $display( "**** EOF Requested\n ");
punk@50 504 let sample = inAudioFifo.first();
punk@50 505 case (sample) matches
punk@50 506 tagged EndOfFile :
punk@50 507 begin
punk@50 508 $display("PROCESSOR sent toC EOF");
punk@50 509 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(True)) }); // Reading clears bit
punk@50 510 inAudioFifo.deq;
punk@50 511 end
punk@50 512 tagged Sample .data:
punk@50 513 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(False)) }); // Reading clears bit
punk@50 514 endcase
punk@36 515 end
punk@36 516 5'd28 : begin
punk@36 517 $display( "***** Reqesting Sample \n");
punk@36 518 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
punk@36 519 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
punk@50 520 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
punk@36 521 else $display ( "Audio File EOF Reached. Invalid sample request.");
punk@36 522 inAudioFifo.deq();
punk@36 523 end
punk@26 524 default :
punk@26 525 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
punk@26 526 endcase
punk@26 527 end
punk@26 528
punk@26 529 // -- Illegal ---------------------------------------------------
punk@26 530
punk@26 531 default :
punk@26 532 $display( " RTL-ERROR : %m : Illegal instruction !" );
punk@26 533
punk@26 534 endcase
punk@26 535
punk@26 536 //evaluate branch prediction
punk@26 537 Addr ppc = pcQ.first().qnxtpc; //predicted branch
punk@26 538 if (ppc != newPC) //prediction wrong
punk@26 539 begin
punk@26 540 epoch <= pcQ.first().qepoch + 1;
punk@26 541 bp.upd(instrpc, newPC); //update branch predictor
punk@26 542 pcQ.clear();
punk@26 543 pc <= newPC;
punk@26 544 end
punk@26 545 else
punk@26 546 pcQ.deq();
punk@26 547
punk@26 548 if ( cp0_statsEn )
punk@26 549 num_inst.incr();
punk@26 550
punk@26 551 endrule
punk@26 552
punk@26 553 rule writeback; // ( stage == Writeback );
punk@26 554 traceTiny("mkProc", "writeback","W");
punk@26 555
punk@26 556
punk@26 557 // get what to do off the writeback queue
punk@26 558 wbQ.deq();
punk@26 559 case (wbQ.first()) matches
punk@26 560 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
punk@26 561 tagged WB_Load .regWr :
punk@26 562 begin
punk@26 563 dataRespQ.deq();
punk@26 564 if (dataRespQ.first() matches tagged LoadResp .ld)
punk@26 565 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
punk@26 566 end
punk@26 567 tagged WB_Store : dataRespQ.deq();
punk@26 568 tagged WB_Host .dat : noAction;
punk@26 569 endcase
punk@26 570
punk@26 571 endrule
punk@26 572
punk@26 573 rule inc_num_cycles;
punk@26 574 if ( cp0_statsEn )
punk@26 575 num_cycles.incr();
punk@26 576 endrule
punk@26 577
punk@50 578 /*
punk@36 579 // for now, we don't do anything.
punk@50 580 rule connectAudioReqResp;
punk@50 581 $display("rlm: PROCESSOR copies a datum\n");
punk@50 582 outAudioFifo.enq(inAudioFifo.first());
punk@50 583 inAudioFifo.deq;
punk@50 584 endrule
punk@50 585 */
punk@50 586 /*
punk@36 587 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
punk@50 588 $display (" PROCESSOR End Audio Flag Set ");
punk@36 589 cp0_audioEOF <= True;
punk@36 590 inAudioFifo.deq;
punk@26 591 endrule
punk@50 592 */
punk@50 593 rule sendProcEnd (cp0_progComp);
punk@36 594 $display (" PROCESSOR Says Program Complete ");
punk@36 595 outAudioFifo.enq(tagged EndOfFile);
punk@36 596 cp0_progComp <= False; //only send one. And functions to reset
punk@26 597 endrule
punk@26 598
punk@26 599
punk@26 600 //-----------------------------------------------------------
punk@26 601 // Methods
punk@26 602
punk@26 603 interface Client imem_client;
punk@26 604 interface Get request = fifoToGet(instReqQ);
punk@26 605 interface Put response = fifoToPut(instRespQ);
punk@26 606 endinterface
punk@26 607
punk@26 608 interface Client dmem_client;
punk@26 609 interface Get request = fifoToGet(dataReqQ);
punk@26 610 interface Put response = fifoToPut(dataRespQ);
punk@26 611 endinterface
punk@26 612
punk@26 613 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
punk@26 614
punk@36 615 /*
punk@36 616 interface CPUToHost tohost;
punk@36 617 method Bit#(32) cpuToHost(int req);
punk@36 618 return (case (req)
punk@36 619 0: cp0_tohost;
punk@36 620 1: pc;
punk@36 621 2: zeroExtend(pack(stage));
punk@36 622 endcase);
punk@36 623 endmethod
punk@36 624 endinterface
punk@36 625 */
punk@36 626
punk@26 627 interface Get sampleOutput = fifoToGet(outAudioFifo);
punk@36 628 interface Put sampleInput = fifoToPut(inAudioFifo);
punk@26 629
punk@26 630 endmodule
punk@26 631