pygar: modules/bluespec/Pygar/core/Processor.bsv annotate

annotate modules/bluespec/Pygar/core/Processor.bsv @ 36:99519a031813 pygar svn.37

[svn r37] moved the server into audioCorePipeline

author	punk
date	Tue, 04 May 2010 18:54:54 -0400
parents	14f7a7ace3f5
children	0475235d1513

rev	line source
rlm@8	1 /// The MIT License
rlm@8	2
rlm@8	3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8	4
rlm@8	5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8	6 // of this software and associated documentation files (the "Software"), to deal
rlm@8	7 // in the Software without restriction, including without limitation the rights
rlm@8	8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8	9 // copies of the Software, and to permit persons to whom the Software is
rlm@8	10 // furnished to do so, subject to the following conditions:
rlm@8	11
rlm@8	12 // The above copyright notice and this permission notice shall be included in
rlm@8	13 // all copies or substantial portions of the Software.
rlm@8	14
rlm@8	15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8	16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8	17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8	18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8	19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8	20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8	21 // THE SOFTWARE.
rlm@8	22
rlm@19	23
rlm@8	24 import Connectable::*;
rlm@8	25 import GetPut::*;
rlm@8	26 import ClientServer::*;
rlm@8	27 import RegFile::*;
rlm@8	28
rlm@8	29 import FIFO::*;
rlm@8	30 import FIFOF::*;
rlm@8	31 import SFIFO::*;
rlm@8	32 import RWire::*;
rlm@8	33
punk@11	34 import Trace::*;
rlm@8	35 import BFIFO::*;
rlm@8	36 import MemTypes::*;
rlm@8	37 import ProcTypes::*;
rlm@8	38 import BRegFile::*;
rlm@8	39 import BranchPred::*;
rlm@8	40 //import PathTypes::*; This is only there to force the debugging
rlm@8	41
rlm@8	42 //AWB includes
rlm@8	43 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8	44 `include "asim/provides/soft_connections.bsh"
rlm@8	45 `include "asim/provides/common_services.bsh"
rlm@8	46
rlm@8	47 // Local includes
punk@11	48 //`include "asim/provides/processor_library.bsh" (included above directly)
punk@36	49
rlm@8	50 `include "asim/provides/common_services.bsh"
rlm@8	51 `include "asim/dict/STATS_PROCESSOR.bsh"
punk@26	52 `include "asim/provides/processor_library.bsh"
rlm@8	53
punk@11	54 // Local includes. Look for the correspondingly named .awb files
punk@11	55 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@11	56 // to find the actual Bluespec files which are used to generate
punk@11	57 // these includes. These files are specific to this audio processing
punk@11	58 // pipeline
punk@11	59
punk@12	60 `include "asim/provides/audio_pipe_types.bsh"
rlm@8	61
punk@12	62 //interface CPUToHost;
punk@12	63 // method Bit#(32) cpuToHost(int req);
punk@12	64 //endinterface
rlm@8	65
rlm@8	66 interface Proc;
rlm@8	67
rlm@8	68 // Interface from processor to caches
rlm@8	69 interface Client#(DataReq,DataResp) dmem_client;
rlm@8	70 interface Client#(InstReq,InstResp) imem_client;
rlm@8	71
rlm@8	72 // Interface for enabling/disabling statistics on the rest of the core
rlm@8	73 interface Get#(Bool) statsEn_get;
rlm@8	74
punk@12	75 // // Interface to host
punk@12	76 // interface CPUToHost tohost;
rlm@8	77
punk@11	78 // Interface to Audio Pipeline
punk@15	79 interface Get#(AudioProcessorUnit) sampleOutput;
punk@36	80 interface Put#(AudioProcessorUnit) sampleInput;
punk@11	81
rlm@8	82 endinterface
rlm@8	83
punk@11	84 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
punk@15	85 //interface AudioOut;
punk@15	86 // interface Get#(AudioProcessorUnit) audioSampleOutput;
punk@15	87 //endinterface
rlm@8	88
punk@12	89 //interface AudioIn;
punk@12	90 // interface Put#(AudioProcessorUnit) audioSampleInput;
punk@12	91 //endinterface
punk@12	92
rlm@8	93 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
rlm@8	94
rlm@8	95 //-----------------------------------------------------------
rlm@8	96 // Register file module
rlm@8	97 //-----------------------------------------------------------
rlm@8	98
rlm@8	99 interface BRFile;
rlm@8	100 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	101 method Bit#(32) rd1( Rindx rindx );
rlm@8	102 method Bit#(32) rd2( Rindx rindx );
rlm@8	103 endinterface
rlm@8	104
rlm@8	105 module mkBRFile( BRFile );
rlm@8	106
rlm@8	107 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
rlm@8	108
rlm@8	109 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	110 rfile.upd( rindx, data );
rlm@8	111 endmethod
rlm@8	112
rlm@8	113 method Bit#(32) rd1( Rindx rindx );
rlm@8	114 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	115 endmethod
rlm@8	116
rlm@8	117 method Bit#(32) rd2( Rindx rindx );
rlm@8	118 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	119 endmethod
rlm@8	120
rlm@8	121 endmodule
rlm@8	122
rlm@8	123 //-----------------------------------------------------------
rlm@8	124 // Helper functions
rlm@8	125 //-----------------------------------------------------------
rlm@8	126
rlm@8	127 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
rlm@8	128 return zeroExtend( pack( signedLT(val1,val2) ) );
rlm@8	129 endfunction
rlm@8	130
rlm@8	131 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
rlm@8	132 return zeroExtend( pack( val1 < val2 ) );
rlm@8	133 endfunction
rlm@8	134
rlm@8	135 function Bit#(32) rshft( Bit#(32) val );
rlm@8	136 return zeroExtend(val[4:0]);
rlm@8	137 endfunction
rlm@8	138
rlm@8	139
rlm@8	140 //-----------------------------------------------------------
rlm@8	141 // Find funct for wbQ
rlm@8	142 //-----------------------------------------------------------
rlm@8	143 function Bool findwbf(Rindx fVal, WBResult cmpVal);
rlm@8	144 case (cmpVal) matches
rlm@8	145 tagged WB_ALU {data:.res, dest:.rd} :
rlm@8	146 return (fVal == rd);
rlm@8	147 tagged WB_Load .rd :
rlm@8	148 return (fVal == rd);
rlm@8	149 tagged WB_Store .st :
rlm@8	150 return False;
rlm@8	151 tagged WB_Host .x :
rlm@8	152 return False;
rlm@8	153 endcase
rlm@8	154 endfunction
rlm@8	155
rlm@8	156
rlm@8	157 //-----------------------------------------------------------
rlm@8	158 // Stall funct for wbQ
rlm@8	159 //-----------------------------------------------------------
rlm@8	160 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
rlm@8	161 case (inst) matches
rlm@8	162 // -- Memory Ops ------------------------------------------------
rlm@8	163 tagged LW .it :
rlm@8	164 return f.find(it.rbase);
rlm@8	165 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
rlm@8	166 return (f.find(addr) \|\| f.find2(dreg));
rlm@8	167
rlm@8	168 // -- Simple Ops ------------------------------------------------
rlm@8	169 tagged ADDIU .it : return f.find(it.rsrc);
rlm@8	170 tagged SLTI .it : return f.find(it.rsrc);
rlm@8	171 tagged SLTIU .it : return f.find(it.rsrc);
rlm@8	172 tagged ANDI .it : return f.find(it.rsrc);
rlm@8	173 tagged ORI .it : return f.find(it.rsrc);
rlm@8	174 tagged XORI .it : return f.find(it.rsrc);
rlm@8	175
rlm@8	176 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
rlm@8	177 tagged SLL .it : return f.find(it.rsrc);
rlm@8	178 tagged SRL .it : return f.find(it.rsrc);
rlm@8	179 tagged SRA .it : return f.find(it.rsrc);
rlm@8	180 tagged SLLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	181 tagged SRLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	182 tagged SRAV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	183 tagged ADDU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	184 tagged SUBU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	185 tagged AND .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	186 tagged OR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	187 tagged XOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	188 tagged NOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	189 tagged SLT .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	190 tagged SLTU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	191
rlm@8	192
rlm@8	193 // -- Branches --------------------------------------------------
rlm@8	194
rlm@8	195 tagged BLEZ .it : return (f.find(it.rsrc));
rlm@8	196 tagged BGTZ .it : return (f.find(it.rsrc));
rlm@8	197 tagged BLTZ .it : return (f.find(it.rsrc));
rlm@8	198 tagged BGEZ .it : return (f.find(it.rsrc));
rlm@8	199 tagged BEQ .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	200 tagged BNE .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	201
rlm@8	202 // -- Jumps -----------------------------------------------------
rlm@8	203
rlm@8	204 tagged J .it : return False;
rlm@8	205 tagged JR .it : return f.find(it.rsrc);
rlm@8	206 tagged JALR .it : return f.find(it.rsrc);
rlm@8	207 tagged JAL .it : return False;
rlm@8	208
rlm@8	209 // -- Cop0 ------------------------------------------------------
rlm@8	210
rlm@8	211 tagged MTC0 .it : return f.find(it.rsrc);
rlm@8	212 tagged MFC0 .it : return False;
rlm@8	213
rlm@8	214 // -- Illegal ---------------------------------------------------
rlm@8	215
rlm@8	216 default : return False;
rlm@8	217
rlm@8	218 endcase
rlm@8	219 endfunction
rlm@8	220 //-----------------------------------------------------------
rlm@8	221 // Reference processor
rlm@8	222 //-----------------------------------------------------------
rlm@8	223
rlm@8	224
rlm@8	225 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
rlm@8	226 //(* synthesize *)
rlm@8	227
rlm@8	228 module [CONNECTED_MODULE] mkProc( Proc );
rlm@8	229
rlm@8	230 //-----------------------------------------------------------
rlm@8	231 // State
rlm@8	232
rlm@8	233 // Standard processor state
rlm@8	234
rlm@8	235 Reg#(Addr) pc <- mkReg(32'h00001000);
rlm@8	236 Reg#(Epoch) epoch <- mkReg(0);
rlm@8	237 Reg#(Stage) stage <- mkReg(PCgen);
rlm@8	238 BRFile rf <- mkBRFile;
rlm@8	239
rlm@8	240 // Branch Prediction
rlm@8	241 BranchPred bp <- mkBranchPred();
rlm@8	242 FIFO#(PCStat) execpc <- mkLFIFO();
rlm@8	243
rlm@8	244 // Pipelines
rlm@8	245 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
rlm@8	246 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
rlm@8	247
punk@33	248 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
rlm@8	249 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
rlm@8	250 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
rlm@8	251 Reg#(Bool) cp0_statsEn <- mkReg(False);
punk@33	252 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
punk@33	253 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
punk@33	254
rlm@8	255 // Memory request/response state
rlm@8	256
rlm@8	257 FIFO#(InstReq) instReqQ <- mkBFIFO1();
rlm@8	258 FIFO#(InstResp) instRespQ <- mkFIFO();
rlm@8	259
rlm@8	260 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
rlm@8	261 FIFO#(DataResp) dataRespQ <- mkFIFO();
rlm@8	262
punk@11	263 // Audio I/O
punk@11	264 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
punk@11	265 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
punk@11	266
punk@11	267
punk@11	268 // Statistics state (2010)
rlm@35	269 // Reg#(Stat) num_cycles <- mkReg(0);
rlm@35	270 // Reg#(Stat) num_inst <- mkReg(0);
rlm@8	271
rlm@8	272 //Or:
punk@11	273 // Statistics state
punk@11	274 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
punk@11	275 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
rlm@8	276
rlm@8	277 //-----------------------------------------------------------
rlm@8	278 // Rules
rlm@8	279
rlm@8	280 (* descending_urgency = "exec, pcgen" *)
rlm@8	281 rule pcgen; //( stage == PCgen );
rlm@8	282 let pc_plus4 = pc + 4;
rlm@8	283
rlm@8	284 traceTiny("mkProc", "pc",pc);
rlm@8	285 traceTiny("mkProc", "pcgen","P");
rlm@8	286 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
rlm@8	287
rlm@8	288 let next_pc = bp.get(pc);
rlm@8	289 if (next_pc matches tagged Valid .npc)
rlm@8	290 begin
rlm@8	291 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
rlm@8	292 pc <= npc;
rlm@8	293 end
rlm@8	294 else
rlm@8	295 begin
rlm@8	296 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
rlm@8	297 pc <= pc_plus4;
rlm@8	298 end
rlm@8	299
rlm@8	300 endrule
rlm@8	301
rlm@8	302 rule discard (instRespQ.first() matches tagged LoadResp .ld
rlm@8	303 &&& ld.tag != epoch);
rlm@8	304 traceTiny("mkProc", "stage", "D");
rlm@8	305 instRespQ.deq();
rlm@8	306 endrule
rlm@8	307
rlm@8	308 (* conflict_free = "exec, writeback" *)
rlm@8	309 rule exec (instRespQ.first() matches tagged LoadResp.ld
rlm@8	310 &&& (ld.tag == epoch)
rlm@8	311 &&& unpack(ld.data) matches .inst
rlm@8	312 &&& !stall(inst, wbQ));
rlm@8	313
rlm@8	314 // Some abbreviations
rlm@8	315 let sext = signExtend;
rlm@8	316 let zext = zeroExtend;
rlm@8	317 let sra = signedShiftRight;
rlm@8	318
rlm@8	319 // Get the instruction
rlm@8	320
rlm@8	321 instRespQ.deq();
rlm@8	322 Instr inst
rlm@8	323 = case ( instRespQ.first() ) matches
rlm@8	324 tagged LoadResp .ld : return unpack(ld.data);
rlm@8	325 tagged StoreResp .st : return ?;
rlm@8	326 endcase;
rlm@8	327
rlm@8	328 // Get the PC info
rlm@8	329 let instrpc = pcQ.first().qpc;
rlm@8	330 let pc_plus4 = instrpc + 4;
rlm@8	331
rlm@8	332 Bool branchTaken = False;
rlm@8	333 Addr newPC = pc_plus4;
rlm@8	334
rlm@8	335 // Tracing
rlm@8	336 traceTiny("mkProc", "exec","X");
rlm@8	337 traceTiny("mkProc", "exInstTiny",inst);
rlm@8	338 traceFull("mkProc", "exInstFull",inst);
rlm@8	339
rlm@8	340 case ( inst ) matches
rlm@8	341
rlm@8	342 // -- Memory Ops ------------------------------------------------
rlm@8	343
rlm@8	344 tagged LW .it :
rlm@8	345 begin
rlm@8	346 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	347 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
rlm@8	348 wbQ.enq(tagged WB_Load it.rdst);
rlm@8	349 end
rlm@8	350
rlm@8	351 tagged SW .it :
rlm@8	352 begin
rlm@8	353 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	354 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
rlm@8	355 wbQ.enq(tagged WB_Store);
rlm@8	356 end
rlm@8	357
rlm@8	358 // -- Simple Ops ------------------------------------------------
rlm@8	359
rlm@8	360 tagged ADDIU .it :
rlm@8	361 begin
rlm@8	362 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
rlm@8	363 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
rlm@8	364 end
rlm@8	365 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
rlm@8	366 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
rlm@8	367 tagged ANDI .it :
rlm@8	368 begin
rlm@8	369 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	370 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
rlm@8	371 end
rlm@8	372 tagged ORI .it :
rlm@8	373 begin
rlm@8	374 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	375 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) \| zext_it_imm)} );
rlm@8	376 end
rlm@8	377 tagged XORI .it :
rlm@8	378 begin
rlm@8	379 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	380 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
rlm@8	381 end
rlm@8	382 tagged LUI .it :
rlm@8	383 begin
rlm@8	384 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	385 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
rlm@8	386 end
rlm@8	387
rlm@8	388 tagged SLL .it :
rlm@8	389 begin
rlm@8	390 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	391 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
rlm@8	392 end
rlm@8	393 tagged SRL .it :
rlm@8	394 begin
rlm@8	395 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	396 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
rlm@8	397 end
rlm@8	398 tagged SRA .it :
rlm@8	399 begin
rlm@8	400 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	401 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
rlm@8	402 end
rlm@8	403 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
rlm@8	404 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
rlm@8	405 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
rlm@8	406 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
rlm@8	407 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
rlm@8	408 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
rlm@8	409 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2) )} );
rlm@8	410 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
rlm@8	411 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2)) )} );
rlm@8	412 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	413 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	414
rlm@8	415 // -- Branches --------------------------------------------------
rlm@8	416
rlm@8	417 tagged BLEZ .it :
rlm@8	418 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
rlm@8	419 begin
rlm@8	420 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	421 branchTaken = True;
rlm@8	422 end
rlm@8	423
rlm@8	424 tagged BGTZ .it :
rlm@8	425 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
rlm@8	426 begin
rlm@8	427 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	428 branchTaken = True;
rlm@8	429 end
rlm@8	430
rlm@8	431 tagged BLTZ .it :
rlm@8	432 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
rlm@8	433 begin
rlm@8	434 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	435 branchTaken = True;
rlm@8	436 end
rlm@8	437
rlm@8	438 tagged BGEZ .it :
rlm@8	439 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
rlm@8	440 begin
rlm@8	441 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	442 branchTaken = True;
rlm@8	443 end
rlm@8	444
rlm@8	445 tagged BEQ .it :
rlm@8	446 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
rlm@8	447 begin
rlm@8	448 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	449 branchTaken = True;
rlm@8	450 end
rlm@8	451
rlm@8	452 tagged BNE .it :
rlm@8	453 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
rlm@8	454 begin
rlm@8	455 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	456 branchTaken = True;
rlm@8	457 end
rlm@8	458
rlm@8	459 // -- Jumps -----------------------------------------------------
rlm@8	460
rlm@8	461 tagged J .it :
rlm@8	462 begin
rlm@8	463 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	464 branchTaken = True;
rlm@8	465 end
rlm@8	466
rlm@8	467 tagged JR .it :
rlm@8	468 begin
rlm@8	469 newPC = rf.rd1(it.rsrc);
rlm@8	470 branchTaken = True;
rlm@8	471 end
rlm@8	472
rlm@8	473 tagged JAL .it :
rlm@8	474 begin
rlm@8	475 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
rlm@8	476 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	477 branchTaken = True;
rlm@8	478 end
rlm@8	479
rlm@8	480 tagged JALR .it :
rlm@8	481 begin
rlm@8	482 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
rlm@8	483 newPC = rf.rd1(it.rsrc);
rlm@8	484 branchTaken = True;
rlm@8	485 end
rlm@8	486
rlm@8	487 // -- Cop0 ------------------------------------------------------
rlm@8	488
punk@33	489 tagged MTC0 .it : //Recieve things from host computer
rlm@8	490 begin
punk@33	491 $display( " PROCESSOR MTC0 call\n");
rlm@8	492 case ( it.cop0dst )
rlm@8	493 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
rlm@8	494 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
punk@33	495 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
punk@33	496 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32
rlm@8	497 default :
rlm@8	498 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
rlm@8	499 endcase
rlm@8	500 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
rlm@8	501 end
rlm@8	502
rlm@8	503 //this is host stuff?
punk@33	504 tagged MFC0 .it : //Things out
rlm@8	505 begin
punk@33	506 $display( " PROCESSOR MFC0 call\n");
rlm@8	507 case ( it.cop0src )
rlm@8	508 // not actually an ALU instruction but don't have the format otherwise
rlm@8	509 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
rlm@8	510 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
rlm@8	511 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
punk@33	512 5'd25 : begin
punk@33	513 $display( "**** EOF Requested\n ");
punk@33	514 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit
punk@33	515 cp0_audioEOF <= False;
punk@33	516 end
punk@33	517 5'd28 : begin
punk@33	518 $display( "***** Reqesting Sample \n");
punk@33	519 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
punk@33	520 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
punk@33	521 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
punk@33	522 else $display ( "Audio File EOF Reached. Invalid sample request.");
punk@33	523 inAudioFifo.deq();
punk@33	524 end
rlm@8	525 default :
rlm@8	526 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
rlm@8	527 endcase
rlm@8	528 end
rlm@8	529
rlm@8	530 // -- Illegal ---------------------------------------------------
rlm@8	531
rlm@8	532 default :
rlm@8	533 $display( " RTL-ERROR : %m : Illegal instruction !" );
rlm@8	534
rlm@8	535 endcase
rlm@8	536
rlm@8	537 //evaluate branch prediction
rlm@8	538 Addr ppc = pcQ.first().qnxtpc; //predicted branch
rlm@8	539 if (ppc != newPC) //prediction wrong
rlm@8	540 begin
rlm@8	541 epoch <= pcQ.first().qepoch + 1;
rlm@8	542 bp.upd(instrpc, newPC); //update branch predictor
rlm@8	543 pcQ.clear();
rlm@8	544 pc <= newPC;
rlm@8	545 end
rlm@8	546 else
rlm@8	547 pcQ.deq();
rlm@8	548
rlm@8	549 if ( cp0_statsEn )
punk@11	550 num_inst.incr();
rlm@8	551
rlm@8	552 endrule
rlm@8	553
rlm@8	554 rule writeback; // ( stage == Writeback );
rlm@8	555 traceTiny("mkProc", "writeback","W");
rlm@8	556
rlm@8	557
rlm@8	558 // get what to do off the writeback queue
rlm@8	559 wbQ.deq();
rlm@8	560 case (wbQ.first()) matches
rlm@8	561 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
rlm@8	562 tagged WB_Load .regWr :
rlm@8	563 begin
rlm@8	564 dataRespQ.deq();
rlm@8	565 if (dataRespQ.first() matches tagged LoadResp .ld)
rlm@8	566 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
rlm@8	567 end
rlm@8	568 tagged WB_Store : dataRespQ.deq();
rlm@8	569 tagged WB_Host .dat : noAction;
rlm@8	570 endcase
rlm@8	571
rlm@8	572 endrule
rlm@8	573
rlm@8	574 rule inc_num_cycles;
rlm@8	575 if ( cp0_statsEn )
punk@11	576 num_cycles.incr();
rlm@8	577 endrule
punk@11	578
punk@11	579
punk@11	580 // for now, we don't do anything.
punk@33	581 // rule connectAudioReqResp;
punk@25	582 // $display("rlm: PROCESSOR copies a datum\n");
punk@33	583 // outAudioFifo.enq(inAudioFifo.first());
punk@33	584 // inAudioFifo.deq;
punk@33	585 // endrule
punk@33	586
punk@33	587 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
punk@33	588 $display (" Proc Says End Audio Flag Set ");
punk@33	589 cp0_audioEOF <= True;
punk@33	590 inAudioFifo.deq;
punk@33	591 endrule
punk@33	592
punk@33	593 rule sendAudioEnd (cp0_progComp);
punk@33	594 $display (" PROCESSOR Says Program Complete ");
punk@33	595 outAudioFifo.enq(tagged EndOfFile);
punk@33	596 cp0_progComp <= False; //only send one. And functions to reset
punk@11	597 endrule
rlm@8	598
punk@12	599
rlm@8	600 //-----------------------------------------------------------
rlm@8	601 // Methods
rlm@8	602
rlm@8	603 interface Client imem_client;
punk@21	604 interface Get request = fifoToGet(instReqQ);
punk@21	605 interface Put response = fifoToPut(instRespQ);
rlm@8	606 endinterface
rlm@8	607
rlm@8	608 interface Client dmem_client;
punk@21	609 interface Get request = fifoToGet(dataReqQ);
punk@21	610 interface Put response = fifoToPut(dataRespQ);
rlm@8	611 endinterface
rlm@8	612
rlm@8	613 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
rlm@8	614
punk@36	615 /*
punk@36	616 interface CPUToHost tohost;
punk@36	617 method Bit#(32) cpuToHost(int req);
punk@36	618 return (case (req)
punk@36	619 0: cp0_tohost;
punk@36	620 1: pc;
punk@36	621 2: zeroExtend(pack(stage));
punk@36	622 endcase);
punk@36	623 endmethod
punk@36	624 endinterface
punk@36	625 */
punk@36	626
punk@21	627 interface Get sampleOutput = fifoToGet(outAudioFifo);
punk@36	628 interface Put sampleInput = fifoToPut(inAudioFifo);
punk@11	629
rlm@8	630 endmodule
rlm@8	631

Mercurial > pygar

annotate modules/bluespec/Pygar/core/Processor.bsv @ 36:99519a031813 pygar svn.37