view modules/bluespec/Pygar/core/Processor.bsv @ 36:99519a031813 pygar svn.37

[svn r37] moved the server into audioCorePipeline
author punk
date Tue, 04 May 2010 18:54:54 -0400
parents 14f7a7ace3f5
children 0475235d1513
line wrap: on
line source
1 /// The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
24 import Connectable::*;
25 import GetPut::*;
26 import ClientServer::*;
27 import RegFile::*;
29 import FIFO::*;
30 import FIFOF::*;
31 import SFIFO::*;
32 import RWire::*;
34 import Trace::*;
35 import BFIFO::*;
36 import MemTypes::*;
37 import ProcTypes::*;
38 import BRegFile::*;
39 import BranchPred::*;
40 //import PathTypes::*; This is only there to force the debugging
42 //AWB includes
43 `include "asim/provides/low_level_platform_interface.bsh"
44 `include "asim/provides/soft_connections.bsh"
45 `include "asim/provides/common_services.bsh"
47 // Local includes
48 //`include "asim/provides/processor_library.bsh" (included above directly)
50 `include "asim/provides/common_services.bsh"
51 `include "asim/dict/STATS_PROCESSOR.bsh"
52 `include "asim/provides/processor_library.bsh"
54 // Local includes. Look for the correspondingly named .awb files
55 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
56 // to find the actual Bluespec files which are used to generate
57 // these includes. These files are specific to this audio processing
58 // pipeline
60 `include "asim/provides/audio_pipe_types.bsh"
62 //interface CPUToHost;
63 // method Bit#(32) cpuToHost(int req);
64 //endinterface
66 interface Proc;
68 // Interface from processor to caches
69 interface Client#(DataReq,DataResp) dmem_client;
70 interface Client#(InstReq,InstResp) imem_client;
72 // Interface for enabling/disabling statistics on the rest of the core
73 interface Get#(Bool) statsEn_get;
75 // // Interface to host
76 // interface CPUToHost tohost;
78 // Interface to Audio Pipeline
79 interface Get#(AudioProcessorUnit) sampleOutput;
80 interface Put#(AudioProcessorUnit) sampleInput;
82 endinterface
84 //The full interface for this is as below in the common file for audioProcessorTypes.bsv
85 //interface AudioOut;
86 // interface Get#(AudioProcessorUnit) audioSampleOutput;
87 //endinterface
89 //interface AudioIn;
90 // interface Put#(AudioProcessorUnit) audioSampleInput;
91 //endinterface
93 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
95 //-----------------------------------------------------------
96 // Register file module
97 //-----------------------------------------------------------
99 interface BRFile;
100 method Action wr( Rindx rindx, Bit#(32) data );
101 method Bit#(32) rd1( Rindx rindx );
102 method Bit#(32) rd2( Rindx rindx );
103 endinterface
105 module mkBRFile( BRFile );
107 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
109 method Action wr( Rindx rindx, Bit#(32) data );
110 rfile.upd( rindx, data );
111 endmethod
113 method Bit#(32) rd1( Rindx rindx );
114 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
115 endmethod
117 method Bit#(32) rd2( Rindx rindx );
118 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
119 endmethod
121 endmodule
123 //-----------------------------------------------------------
124 // Helper functions
125 //-----------------------------------------------------------
127 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
128 return zeroExtend( pack( signedLT(val1,val2) ) );
129 endfunction
131 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
132 return zeroExtend( pack( val1 < val2 ) );
133 endfunction
135 function Bit#(32) rshft( Bit#(32) val );
136 return zeroExtend(val[4:0]);
137 endfunction
140 //-----------------------------------------------------------
141 // Find funct for wbQ
142 //-----------------------------------------------------------
143 function Bool findwbf(Rindx fVal, WBResult cmpVal);
144 case (cmpVal) matches
145 tagged WB_ALU {data:.res, dest:.rd} :
146 return (fVal == rd);
147 tagged WB_Load .rd :
148 return (fVal == rd);
149 tagged WB_Store .st :
150 return False;
151 tagged WB_Host .x :
152 return False;
153 endcase
154 endfunction
157 //-----------------------------------------------------------
158 // Stall funct for wbQ
159 //-----------------------------------------------------------
160 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
161 case (inst) matches
162 // -- Memory Ops ------------------------------------------------
163 tagged LW .it :
164 return f.find(it.rbase);
165 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
166 return (f.find(addr) || f.find2(dreg));
168 // -- Simple Ops ------------------------------------------------
169 tagged ADDIU .it : return f.find(it.rsrc);
170 tagged SLTI .it : return f.find(it.rsrc);
171 tagged SLTIU .it : return f.find(it.rsrc);
172 tagged ANDI .it : return f.find(it.rsrc);
173 tagged ORI .it : return f.find(it.rsrc);
174 tagged XORI .it : return f.find(it.rsrc);
176 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
177 tagged SLL .it : return f.find(it.rsrc);
178 tagged SRL .it : return f.find(it.rsrc);
179 tagged SRA .it : return f.find(it.rsrc);
180 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
181 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
182 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
183 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
184 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
185 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
186 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
187 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
188 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
189 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
190 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
193 // -- Branches --------------------------------------------------
195 tagged BLEZ .it : return (f.find(it.rsrc));
196 tagged BGTZ .it : return (f.find(it.rsrc));
197 tagged BLTZ .it : return (f.find(it.rsrc));
198 tagged BGEZ .it : return (f.find(it.rsrc));
199 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
200 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
202 // -- Jumps -----------------------------------------------------
204 tagged J .it : return False;
205 tagged JR .it : return f.find(it.rsrc);
206 tagged JALR .it : return f.find(it.rsrc);
207 tagged JAL .it : return False;
209 // -- Cop0 ------------------------------------------------------
211 tagged MTC0 .it : return f.find(it.rsrc);
212 tagged MFC0 .it : return False;
214 // -- Illegal ---------------------------------------------------
216 default : return False;
218 endcase
219 endfunction
220 //-----------------------------------------------------------
221 // Reference processor
222 //-----------------------------------------------------------
225 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
226 //(* synthesize *)
228 module [CONNECTED_MODULE] mkProc( Proc );
230 //-----------------------------------------------------------
231 // State
233 // Standard processor state
235 Reg#(Addr) pc <- mkReg(32'h00001000);
236 Reg#(Epoch) epoch <- mkReg(0);
237 Reg#(Stage) stage <- mkReg(PCgen);
238 BRFile rf <- mkBRFile;
240 // Branch Prediction
241 BranchPred bp <- mkBranchPred();
242 FIFO#(PCStat) execpc <- mkLFIFO();
244 // Pipelines
245 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
246 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
248 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
249 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
250 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
251 Reg#(Bool) cp0_statsEn <- mkReg(False);
252 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
253 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
255 // Memory request/response state
257 FIFO#(InstReq) instReqQ <- mkBFIFO1();
258 FIFO#(InstResp) instRespQ <- mkFIFO();
260 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
261 FIFO#(DataResp) dataRespQ <- mkFIFO();
263 // Audio I/O
264 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
265 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
268 // Statistics state (2010)
269 // Reg#(Stat) num_cycles <- mkReg(0);
270 // Reg#(Stat) num_inst <- mkReg(0);
272 //Or:
273 // Statistics state
274 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
275 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
277 //-----------------------------------------------------------
278 // Rules
280 (* descending_urgency = "exec, pcgen" *)
281 rule pcgen; //( stage == PCgen );
282 let pc_plus4 = pc + 4;
284 traceTiny("mkProc", "pc",pc);
285 traceTiny("mkProc", "pcgen","P");
286 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
288 let next_pc = bp.get(pc);
289 if (next_pc matches tagged Valid .npc)
290 begin
291 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
292 pc <= npc;
293 end
294 else
295 begin
296 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
297 pc <= pc_plus4;
298 end
300 endrule
302 rule discard (instRespQ.first() matches tagged LoadResp .ld
303 &&& ld.tag != epoch);
304 traceTiny("mkProc", "stage", "D");
305 instRespQ.deq();
306 endrule
308 (* conflict_free = "exec, writeback" *)
309 rule exec (instRespQ.first() matches tagged LoadResp.ld
310 &&& (ld.tag == epoch)
311 &&& unpack(ld.data) matches .inst
312 &&& !stall(inst, wbQ));
314 // Some abbreviations
315 let sext = signExtend;
316 let zext = zeroExtend;
317 let sra = signedShiftRight;
319 // Get the instruction
321 instRespQ.deq();
322 Instr inst
323 = case ( instRespQ.first() ) matches
324 tagged LoadResp .ld : return unpack(ld.data);
325 tagged StoreResp .st : return ?;
326 endcase;
328 // Get the PC info
329 let instrpc = pcQ.first().qpc;
330 let pc_plus4 = instrpc + 4;
332 Bool branchTaken = False;
333 Addr newPC = pc_plus4;
335 // Tracing
336 traceTiny("mkProc", "exec","X");
337 traceTiny("mkProc", "exInstTiny",inst);
338 traceFull("mkProc", "exInstFull",inst);
340 case ( inst ) matches
342 // -- Memory Ops ------------------------------------------------
344 tagged LW .it :
345 begin
346 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
347 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
348 wbQ.enq(tagged WB_Load it.rdst);
349 end
351 tagged SW .it :
352 begin
353 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
354 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
355 wbQ.enq(tagged WB_Store);
356 end
358 // -- Simple Ops ------------------------------------------------
360 tagged ADDIU .it :
361 begin
362 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
363 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
364 end
365 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
366 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
367 tagged ANDI .it :
368 begin
369 Bit#(32) zext_it_imm = zext(it.imm);
370 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
371 end
372 tagged ORI .it :
373 begin
374 Bit#(32) zext_it_imm = zext(it.imm);
375 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
376 end
377 tagged XORI .it :
378 begin
379 Bit#(32) zext_it_imm = zext(it.imm);
380 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
381 end
382 tagged LUI .it :
383 begin
384 Bit#(32) zext_it_imm = zext(it.imm);
385 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
386 end
388 tagged SLL .it :
389 begin
390 Bit#(32) zext_it_shamt = zext(it.shamt);
391 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
392 end
393 tagged SRL .it :
394 begin
395 Bit#(32) zext_it_shamt = zext(it.shamt);
396 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
397 end
398 tagged SRA .it :
399 begin
400 Bit#(32) zext_it_shamt = zext(it.shamt);
401 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
402 end
403 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
404 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
405 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
406 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
407 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
408 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
409 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
410 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
411 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
412 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
413 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
415 // -- Branches --------------------------------------------------
417 tagged BLEZ .it :
418 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
419 begin
420 newPC = pc_plus4 + (sext(it.offset) << 2);
421 branchTaken = True;
422 end
424 tagged BGTZ .it :
425 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
426 begin
427 newPC = pc_plus4 + (sext(it.offset) << 2);
428 branchTaken = True;
429 end
431 tagged BLTZ .it :
432 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
433 begin
434 newPC = pc_plus4 + (sext(it.offset) << 2);
435 branchTaken = True;
436 end
438 tagged BGEZ .it :
439 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
440 begin
441 newPC = pc_plus4 + (sext(it.offset) << 2);
442 branchTaken = True;
443 end
445 tagged BEQ .it :
446 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
447 begin
448 newPC = pc_plus4 + (sext(it.offset) << 2);
449 branchTaken = True;
450 end
452 tagged BNE .it :
453 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
454 begin
455 newPC = pc_plus4 + (sext(it.offset) << 2);
456 branchTaken = True;
457 end
459 // -- Jumps -----------------------------------------------------
461 tagged J .it :
462 begin
463 newPC = { pc_plus4[31:28], it.target, 2'b0 };
464 branchTaken = True;
465 end
467 tagged JR .it :
468 begin
469 newPC = rf.rd1(it.rsrc);
470 branchTaken = True;
471 end
473 tagged JAL .it :
474 begin
475 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
476 newPC = { pc_plus4[31:28], it.target, 2'b0 };
477 branchTaken = True;
478 end
480 tagged JALR .it :
481 begin
482 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
483 newPC = rf.rd1(it.rsrc);
484 branchTaken = True;
485 end
487 // -- Cop0 ------------------------------------------------------
489 tagged MTC0 .it : //Recieve things from host computer
490 begin
491 $display( " PROCESSOR MTC0 call\n");
492 case ( it.cop0dst )
493 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
494 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
495 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
496 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32
497 default :
498 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
499 endcase
500 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
501 end
503 //this is host stuff?
504 tagged MFC0 .it : //Things out
505 begin
506 $display( " PROCESSOR MFC0 call\n");
507 case ( it.cop0src )
508 // not actually an ALU instruction but don't have the format otherwise
509 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
510 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
511 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
512 5'd25 : begin
513 $display( "**** EOF Requested\n ");
514 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit
515 cp0_audioEOF <= False;
516 end
517 5'd28 : begin
518 $display( "***** Reqesting Sample \n");
519 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
520 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
521 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
522 else $display ( "Audio File EOF Reached. Invalid sample request.");
523 inAudioFifo.deq();
524 end
525 default :
526 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
527 endcase
528 end
530 // -- Illegal ---------------------------------------------------
532 default :
533 $display( " RTL-ERROR : %m : Illegal instruction !" );
535 endcase
537 //evaluate branch prediction
538 Addr ppc = pcQ.first().qnxtpc; //predicted branch
539 if (ppc != newPC) //prediction wrong
540 begin
541 epoch <= pcQ.first().qepoch + 1;
542 bp.upd(instrpc, newPC); //update branch predictor
543 pcQ.clear();
544 pc <= newPC;
545 end
546 else
547 pcQ.deq();
549 if ( cp0_statsEn )
550 num_inst.incr();
552 endrule
554 rule writeback; // ( stage == Writeback );
555 traceTiny("mkProc", "writeback","W");
558 // get what to do off the writeback queue
559 wbQ.deq();
560 case (wbQ.first()) matches
561 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
562 tagged WB_Load .regWr :
563 begin
564 dataRespQ.deq();
565 if (dataRespQ.first() matches tagged LoadResp .ld)
566 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
567 end
568 tagged WB_Store : dataRespQ.deq();
569 tagged WB_Host .dat : noAction;
570 endcase
572 endrule
574 rule inc_num_cycles;
575 if ( cp0_statsEn )
576 num_cycles.incr();
577 endrule
580 // for now, we don't do anything.
581 // rule connectAudioReqResp;
582 // $display("rlm: PROCESSOR copies a datum\n");
583 // outAudioFifo.enq(inAudioFifo.first());
584 // inAudioFifo.deq;
585 // endrule
587 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
588 $display (" Proc Says End Audio Flag Set ");
589 cp0_audioEOF <= True;
590 inAudioFifo.deq;
591 endrule
593 rule sendAudioEnd (cp0_progComp);
594 $display (" PROCESSOR Says Program Complete ");
595 outAudioFifo.enq(tagged EndOfFile);
596 cp0_progComp <= False; //only send one. And functions to reset
597 endrule
600 //-----------------------------------------------------------
601 // Methods
603 interface Client imem_client;
604 interface Get request = fifoToGet(instReqQ);
605 interface Put response = fifoToPut(instRespQ);
606 endinterface
608 interface Client dmem_client;
609 interface Get request = fifoToGet(dataReqQ);
610 interface Put response = fifoToPut(dataRespQ);
611 endinterface
613 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
615 /*
616 interface CPUToHost tohost;
617 method Bit#(32) cpuToHost(int req);
618 return (case (req)
619 0: cp0_tohost;
620 1: pc;
621 2: zeroExtend(pack(stage));
622 endcase);
623 endmethod
624 endinterface
625 */
627 interface Get sampleOutput = fifoToGet(outAudioFifo);
628 interface Put sampleInput = fifoToPut(inAudioFifo);
630 endmodule