Mercurial > pygar
annotate core/sim/bdir_dut/Bridge.bi @ 1:91a1f76ddd62 pygar svn.2
[svn r2] Adding initial lab 5 source
| author | punk |
|---|---|
| date | Tue, 13 Apr 2010 17:34:33 -0400 |
| parents | |
| children |
| rev | line source |
|---|---|
| punk@1 | 1 signature Bridge where { |
| punk@1 | 2 import ¶Assert®¶; |
| punk@1 | 3 |
| punk@1 | 4 import ¶ConfigReg®¶; |
| punk@1 | 5 |
| punk@1 | 6 import ¶Counter®¶; |
| punk@1 | 7 |
| punk@1 | 8 import ¶DReg®¶; |
| punk@1 | 9 |
| punk@1 | 10 import ¶EdgeDetect®¶; |
| punk@1 | 11 |
| punk@1 | 12 import ¶FIFOF_®¶; |
| punk@1 | 13 |
| punk@1 | 14 import ¶FIFOF®¶; |
| punk@1 | 15 |
| punk@1 | 16 import ¶FIFO®¶; |
| punk@1 | 17 |
| punk@1 | 18 import ¶HList®¶; |
| punk@1 | 19 |
| punk@1 | 20 import ¶Inout®¶; |
| punk@1 | 21 |
| punk@1 | 22 import ¶List®¶; |
| punk@1 | 23 |
| punk@1 | 24 import BFIFO; |
| punk@1 | 25 |
| punk@1 | 26 import ¶Clocks®¶; |
| punk@1 | 27 |
| punk@1 | 28 import ¶DiniPCIE®¶; |
| punk@1 | 29 |
| punk@1 | 30 import ¶ListN®¶; |
| punk@1 | 31 |
| punk@1 | 32 import ¶ModuleContextCore®¶; |
| punk@1 | 33 |
| punk@1 | 34 import ¶ModuleContext®¶; |
| punk@1 | 35 |
| punk@1 | 36 import ¶Monad®¶; |
| punk@1 | 37 |
| punk@1 | 38 import ¶PrimArray®¶; |
| punk@1 | 39 |
| punk@1 | 40 import ¶RWire®¶; |
| punk@1 | 41 |
| punk@1 | 42 import ¶RegFile®¶; |
| punk@1 | 43 |
| punk@1 | 44 import ¶Real®¶; |
| punk@1 | 45 |
| punk@1 | 46 import ¶RevertingVirtualReg®¶; |
| punk@1 | 47 |
| punk@1 | 48 import ¶Reserved®¶; |
| punk@1 | 49 |
| punk@1 | 50 import SFIFO; |
| punk@1 | 51 |
| punk@1 | 52 import ¶Vector®¶; |
| punk@1 | 53 |
| punk@1 | 54 import ¶BRAMCore®¶; |
| punk@1 | 55 |
| punk@1 | 56 import ¶BUtils®¶; |
| punk@1 | 57 |
| punk@1 | 58 import ¶Connectable®¶; |
| punk@1 | 59 |
| punk@1 | 60 import ¶DefaultValue®¶; |
| punk@1 | 61 |
| punk@1 | 62 import ¶Gearbox®¶; |
| punk@1 | 63 |
| punk@1 | 64 import ¶GetPut®¶; |
| punk@1 | 65 |
| punk@1 | 66 import ¶AlignedFIFOs®¶; |
| punk@1 | 67 |
| punk@1 | 68 import ¶ClientServer®¶; |
| punk@1 | 69 |
| punk@1 | 70 import ¶FIFOLevel®¶; |
| punk@1 | 71 |
| punk@1 | 72 import ¶SceMiDefines®¶; |
| punk@1 | 73 |
| punk@1 | 74 import ¶SceMiProxies®¶; |
| punk@1 | 75 |
| punk@1 | 76 import ¶SpecialFIFOs®¶; |
| punk@1 | 77 |
| punk@1 | 78 import ¶SceMiInternals®¶; |
| punk@1 | 79 |
| punk@1 | 80 import ¶SceMiAldecMacros®¶; |
| punk@1 | 81 |
| punk@1 | 82 import ¶SceMiEveMacros®¶; |
| punk@1 | 83 |
| punk@1 | 84 import ¶SceMiMacros®¶; |
| punk@1 | 85 |
| punk@1 | 86 import ¶TieOff®¶; |
| punk@1 | 87 |
| punk@1 | 88 import Trace; |
| punk@1 | 89 |
| punk@1 | 90 import MemTypes; |
| punk@1 | 91 |
| punk@1 | 92 import MemArb; |
| punk@1 | 93 |
| punk@1 | 94 import ProcTypes; |
| punk@1 | 95 |
| punk@1 | 96 import BRegFile; |
| punk@1 | 97 |
| punk@1 | 98 import BranchPred; |
| punk@1 | 99 |
| punk@1 | 100 import DataCacheBlocking; |
| punk@1 | 101 |
| punk@1 | 102 import InstCacheBlocking; |
| punk@1 | 103 |
| punk@1 | 104 import Processor; |
| punk@1 | 105 |
| punk@1 | 106 import Core; |
| punk@1 | 107 |
| punk@1 | 108 import ¶UnitAppendList®¶; |
| punk@1 | 109 |
| punk@1 | 110 import ¶XilinxCells®¶; |
| punk@1 | 111 |
| punk@1 | 112 import ¶SceMiClocks®¶; |
| punk@1 | 113 |
| punk@1 | 114 import ¶SceMiDiniPCIE®¶; |
| punk@1 | 115 |
| punk@1 | 116 import ¶SceMiTCP®¶; |
| punk@1 | 117 |
| punk@1 | 118 import ¶XilinxPCIE®¶; |
| punk@1 | 119 |
| punk@1 | 120 import ¶SceMiVirtex5PCIE®¶; |
| punk@1 | 121 |
| punk@1 | 122 import ¶SceMiPCIE®¶; |
| punk@1 | 123 |
| punk@1 | 124 import ¶SceMiCore®¶; |
| punk@1 | 125 |
| punk@1 | 126 import ¶SceMiXactors®¶; |
| punk@1 | 127 |
| punk@1 | 128 import ¶SceMiSerialProbe®¶; |
| punk@1 | 129 |
| punk@1 | 130 import ¶SceMi®¶; |
| punk@1 | 131 |
| punk@1 | 132 import SceMiLayer; |
| punk@1 | 133 |
| punk@1 | 134 Bridge.lt :: ¶SceMiDefines®¶.¶SceMiLinkType®¶; |
| punk@1 | 135 |
| punk@1 | 136 Bridge.mkBridge :: (¶Prelude®¶.¶IsModule®¶ _m__ _c__) => _m__ ¶Prelude®¶.¶Empty®¶ |
| punk@1 | 137 } |