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1 // The MIT License
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2
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3 // Copyright (c) 2009 Massachusetts Institute of Technology
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4
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5 // Permission is hereby granted, free of charge, to any person obtaining a copy
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6 // of this software and associated documentation files (the "Software"), to deal
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7 // in the Software without restriction, including without limitation the rights
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8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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9 // copies of the Software, and to permit persons to whom the Software is
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10 // furnished to do so, subject to the following conditions:
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11
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12 // The above copyright notice and this permission notice shall be included in
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13 // all copies or substantial portions of the Software.
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14
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15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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21 // THE SOFTWARE.
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22
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23 // Local includes
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24 `include "asim/provides/low_level_platform_interface.bsh"
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25 `include "asim/provides/soft_connections.bsh"
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26 `include "asim/provides/processor_library.bsh"
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27 `include "asim/provides/fpga_components.bsh"
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28 `include "asim/provides/common_services.bsh"
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29
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30 import Connectable::*;
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31 import GetPut::*;
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32 import ClientServer::*;
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33 import RegFile::*;
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34 import FIFO::*;
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35 import FIFOF::*;
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36 import Trace::*;
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37
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38 interface DCache#( type req_t, type resp_t );
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39
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40 // Interface from processor to cache
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41 interface Server#(req_t,resp_t) proc_server;
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42
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43 // Interface from cache to main memory
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44 interface Client#(MainMemReq,MainMemResp) mmem_client;
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45
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46 // Interface for enabling/disabling statistics
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47 interface Put#(Bool) statsEn_put;
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48
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49 endinterface
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50
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51
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52 //----------------------------------------------------------------------
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53 // Cache Types
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54 //----------------------------------------------------------------------
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55
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56 typedef 10 CacheLineIndexSz;
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57 typedef 20 CacheLineTagSz;
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58 typedef 32 CacheLineSz;
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59
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60 typedef Bit#(CacheLineIndexSz) CacheLineIndex;
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61 typedef Bit#(CacheLineTagSz) CacheLineTag;
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62 typedef Bit#(CacheLineSz) CacheLine;
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63
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64 typedef enum
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65 {
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66 Init,
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67 Access,
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68 RefillReq,
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69 RefillResp
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70 }
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71 CacheStage
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72 deriving (Eq,Bits);
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73
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74 //----------------------------------------------------------------------
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75 // Helper functions
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76 //----------------------------------------------------------------------
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77
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78 function Bit#(AddrSz) getAddr( DataReq req );
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79
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80 Bit#(AddrSz) addr = ?;
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81 case ( req ) matches
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82 tagged LoadReq .ld : addr = ld.addr;
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83 tagged StoreReq .st : addr = st.addr;
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84 endcase
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85
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86 return addr;
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87
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88 endfunction
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89
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90 function CacheLineIndex getCacheLineIndex( DataReq req );
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91 Bit#(AddrSz) addr = getAddr(req);
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92 Bit#(CacheLineIndexSz) index = truncate( addr >> 2 );
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93 return index;
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94 endfunction
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95
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96 function CacheLineTag getCacheLineTag( DataReq req );
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97 Bit#(AddrSz) addr = getAddr(req);
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98 Bit#(CacheLineTagSz) tag = truncate( addr >> fromInteger(valueOf(CacheLineIndexSz)) >> 2 );
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99 return tag;
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100 endfunction
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101
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102 function Bit#(AddrSz) getCacheLineAddr( DataReq req );
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103 Bit#(AddrSz) addr = getAddr(req);
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104 return ((addr >> 2) << 2);
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105 endfunction
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106
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107 //----------------------------------------------------------------------
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108 // Main module
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109 //----------------------------------------------------------------------
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110
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111 (* doc = "synthesis attribute ram_style mkDataCache distributed;" *)
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112 (* synthesize *)
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113 module [CONNECTED_MODULE] mkDataCache( DCache#(DataReq,DataResp) );
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114
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115 //-----------------------------------------------------------
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116 // State
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117
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118 Reg#(CacheStage) stage <- mkReg(Init);
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119
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120 LUTRAM#(CacheLineIndex,Maybe#(CacheLineTag)) cacheTagRam <- mkLUTRAMU_RegFile();
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121 LUTRAM#(CacheLineIndex,CacheLine) cacheDataRam <- mkLUTRAMU_RegFile();
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122
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123 FIFO#(DataReq) reqQ <- mkFIFO();
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124 FIFOF#(DataResp) respQ <- mkBFIFOF1();
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125
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126 FIFO#(MainMemReq) mainMemReqQ <- mkBFIFO1();
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127 FIFO#(MainMemResp) mainMemRespQ <- mkFIFO();
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128
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129 Reg#(CacheLineIndex) initCounter <- mkReg(1);
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130
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131 // Statistics state
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132
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133 Reg#(Bool) statsEn <- mkReg(False);
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134 //rlm:
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135 //STAT num_accesses <- mkStatCounter(`STATS_DATA_CACHE_NUM_ACCESSES);
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136 //STAT num_misses <- mkStatCounter(`STATS_DATA_CACHE_NUM_MISSES);
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137 //STAT num_writebacks <- mkStatCounter(`STATS_DATA_CACHE_NUM_WRITEBACKS);
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138
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139 //-----------------------------------------------------------
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140 // Name some wires
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141
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142 let req = reqQ.first();
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143 let reqIndex = getCacheLineIndex(req);
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144 let reqTag = getCacheLineTag(req);
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145 let reqCacheLineAddr = getCacheLineAddr(req);
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146
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147 //-----------------------------------------------------------
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148 // Initialize
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149
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150 rule init ( stage == Init );
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151 traceTiny("mkDataCacheBlocking", "stage","i");
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152 initCounter <= initCounter + 1;
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153 cacheTagRam.upd(initCounter,Invalid);
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154 if ( initCounter == 0 )
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155 stage <= Access;
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156 endrule
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157
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158 //-----------------------------------------------------------
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159 // Access cache rule
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160
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161 rule access ( (stage == Access) && respQ.notFull() );
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162
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163 // Statistics
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164 //rlm:
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165 //if ( statsEn )
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166 // num_accesses.incr();
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167
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168
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169 // Get the corresponding tag from the rams
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170
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171 Maybe#(CacheLineTag) cacheLineTag = cacheTagRam.sub(reqIndex);
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172
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173 // Handle cache hits ...
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174
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175 if ( isValid(cacheLineTag) && ( unJust(cacheLineTag) == reqTag ) )
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176 begin
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177 traceTiny("mkDataCacheBlocking", "hitMiss","h");
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178 reqQ.deq();
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179
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180 case ( req ) matches
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181
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182 tagged LoadReq .ld :
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183 respQ.enq( LoadResp { tag: ld.tag, data: cacheDataRam.sub(reqIndex) } );
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184
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185 tagged StoreReq .st :
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186 begin
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187 respQ.enq( StoreResp { tag : st.tag } );
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188 cacheDataRam.upd(reqIndex,st.data);
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189 end
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190
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191 endcase
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192
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193 end
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194
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195 // Handle cache misses ...
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196
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197 else
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198 begin
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199 traceTiny("mkDataCacheBlocking", "hitMiss","m");
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200 //rlm:
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201 //if ( statsEn )
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202 // num_misses.incr();
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203
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204 // Currently we don't use dirty bits so we always writeback the data if it is valid
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205
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206 if ( isValid(cacheLineTag) )
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207 begin
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208 //rlm:
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209 // if ( statsEn )
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210 // num_writebacks.incr();
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211
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212 MainMemReq wbReq
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213 = StoreReq { tag : 0,
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214 addr : { unJust(cacheLineTag), reqIndex, 2'b0 },
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215 data : cacheDataRam.sub(reqIndex) };
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216
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217 mainMemReqQ.enq(wbReq);
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218 stage <= RefillReq;
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219 end
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220
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221 // Otherwise we can issue the refill request now
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222
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223 else
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224 begin
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225 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
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226 stage <= RefillResp;
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227 end
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228
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229 end
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230
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231 endrule
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232
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233 //-----------------------------------------------------------
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234 // Refill request rule
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235
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236 rule refillReq ( stage == RefillReq );
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237 traceTiny("mkDataCacheBlocking", "stage","r");
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238 mainMemReqQ.enq( LoadReq { tag: 0, addr: reqCacheLineAddr } );
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239 stage <= RefillResp;
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240 endrule
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241
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242 //-----------------------------------------------------------
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243 // Refill response rule
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244
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245 rule refillResp ( stage == RefillResp );
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246 traceTiny("mkDataCacheBlocking", "stage","R");
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247 traceTiny("mkDataCacheBlocking", "refill",mainMemRespQ.first());
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248
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249 // Write the new data into the cache and update the tag
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250
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251 mainMemRespQ.deq();
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252 case ( mainMemRespQ.first() ) matches
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253
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254 tagged LoadResp .ld :
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255 begin
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256 cacheTagRam.upd(reqIndex,Valid(reqTag));
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257 cacheDataRam.upd(reqIndex,ld.data);
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258 end
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259
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260 tagged StoreResp .st :
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261 noAction;
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262
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263 endcase
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264
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265 stage <= Access;
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266 endrule
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267
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268 //-----------------------------------------------------------
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269 // Methods
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270
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271 interface Client mmem_client;
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272 interface Get request = fifoToGet(mainMemReqQ);
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273 interface Put response = fifoToPut(mainMemRespQ);
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274 endinterface
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275
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276 interface Server proc_server;
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277 interface Put request = tracePut("mkDataCacheBlocking", "reqTiny",fifoToPut(reqQ));
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278 interface Get response = traceGet("mkDataCacheBlocking", "respTiny",fifofToGet(respQ));
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279 endinterface
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280
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281 interface Put statsEn_put = regToPut(statsEn);
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282
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283 endmodule
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