pygar: modules/bluespec/Pygar/core/Processor.bsv annotate

annotate modules/bluespec/Pygar/core/Processor.bsv @ 53:2991344775f8 pygar svn.54

[svn r54] mixer integrated

author	punk
date	Sun, 09 May 2010 10:58:40 -0400
parents	9fe5ed4af92d
children	1d5cbb5343d2

rev	line source
punk@51	1 // The MIT License
rlm@8	2
rlm@8	3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8	4
rlm@8	5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8	6 // of this software and associated documentation files (the "Software"), to deal
rlm@8	7 // in the Software without restriction, including without limitation the rights
rlm@8	8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8	9 // copies of the Software, and to permit persons to whom the Software is
rlm@8	10 // furnished to do so, subject to the following conditions:
rlm@8	11
rlm@8	12 // The above copyright notice and this permission notice shall be included in
rlm@8	13 // all copies or substantial portions of the Software.
rlm@8	14
rlm@8	15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8	16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8	17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8	18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8	19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8	20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8	21 // THE SOFTWARE.
rlm@8	22
rlm@19	23
rlm@8	24 import Connectable::*;
rlm@8	25 import GetPut::*;
rlm@8	26 import ClientServer::*;
rlm@8	27 import RegFile::*;
rlm@8	28
rlm@8	29 import FIFO::*;
rlm@8	30 import FIFOF::*;
rlm@8	31 import SFIFO::*;
rlm@8	32 import RWire::*;
rlm@8	33
punk@11	34 import Trace::*;
rlm@8	35 import BFIFO::*;
rlm@8	36 import MemTypes::*;
rlm@8	37 import ProcTypes::*;
rlm@8	38 import BRegFile::*;
rlm@8	39 import BranchPred::*;
rlm@8	40 //import PathTypes::*; This is only there to force the debugging
rlm@8	41
rlm@8	42 //AWB includes
rlm@8	43 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8	44 `include "asim/provides/soft_connections.bsh"
rlm@8	45 `include "asim/provides/common_services.bsh"
rlm@8	46
rlm@8	47 // Local includes
punk@11	48 //`include "asim/provides/processor_library.bsh" (included above directly)
punk@36	49
rlm@8	50 `include "asim/provides/common_services.bsh"
punk@26	51 `include "asim/provides/processor_library.bsh"
rlm@8	52
punk@11	53 // Local includes. Look for the correspondingly named .awb files
punk@11	54 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@11	55 // to find the actual Bluespec files which are used to generate
punk@11	56 // these includes. These files are specific to this audio processing
punk@11	57 // pipeline
punk@11	58
punk@12	59 `include "asim/provides/audio_pipe_types.bsh"
rlm@8	60
punk@12	61 //interface CPUToHost;
punk@12	62 // method Bit#(32) cpuToHost(int req);
punk@12	63 //endinterface
rlm@8	64
rlm@8	65 interface Proc;
rlm@8	66
rlm@8	67 // Interface from processor to caches
rlm@8	68 interface Client#(DataReq,DataResp) dmem_client;
rlm@8	69 interface Client#(InstReq,InstResp) imem_client;
rlm@8	70
rlm@8	71 // Interface for enabling/disabling statistics on the rest of the core
rlm@8	72 interface Get#(Bool) statsEn_get;
rlm@8	73
punk@12	74 // // Interface to host
punk@12	75 // interface CPUToHost tohost;
rlm@8	76
punk@11	77 // Interface to Audio Pipeline
punk@15	78 interface Get#(AudioProcessorUnit) sampleOutput;
punk@36	79 interface Put#(AudioProcessorUnit) sampleInput;
punk@11	80
rlm@8	81 endinterface
rlm@8	82
rlm@8	83 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
rlm@8	84
rlm@8	85 //-----------------------------------------------------------
rlm@8	86 // Register file module
rlm@8	87 //-----------------------------------------------------------
rlm@8	88
rlm@8	89 interface BRFile;
rlm@8	90 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	91 method Bit#(32) rd1( Rindx rindx );
rlm@8	92 method Bit#(32) rd2( Rindx rindx );
rlm@8	93 endinterface
rlm@8	94
rlm@8	95 module mkBRFile( BRFile );
rlm@8	96
rlm@8	97 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
rlm@8	98
rlm@8	99 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8	100 rfile.upd( rindx, data );
rlm@8	101 endmethod
rlm@8	102
rlm@8	103 method Bit#(32) rd1( Rindx rindx );
rlm@8	104 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	105 endmethod
rlm@8	106
rlm@8	107 method Bit#(32) rd2( Rindx rindx );
rlm@8	108 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8	109 endmethod
rlm@8	110
rlm@8	111 endmodule
rlm@8	112
rlm@8	113 //-----------------------------------------------------------
rlm@8	114 // Helper functions
rlm@8	115 //-----------------------------------------------------------
rlm@8	116
rlm@8	117 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
rlm@8	118 return zeroExtend( pack( signedLT(val1,val2) ) );
rlm@8	119 endfunction
rlm@8	120
rlm@8	121 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
rlm@8	122 return zeroExtend( pack( val1 < val2 ) );
rlm@8	123 endfunction
rlm@8	124
rlm@8	125 function Bit#(32) rshft( Bit#(32) val );
rlm@8	126 return zeroExtend(val[4:0]);
rlm@8	127 endfunction
rlm@8	128
rlm@8	129
rlm@8	130 //-----------------------------------------------------------
rlm@8	131 // Find funct for wbQ
rlm@8	132 //-----------------------------------------------------------
rlm@8	133 function Bool findwbf(Rindx fVal, WBResult cmpVal);
rlm@8	134 case (cmpVal) matches
rlm@8	135 tagged WB_ALU {data:.res, dest:.rd} :
rlm@8	136 return (fVal == rd);
rlm@8	137 tagged WB_Load .rd :
rlm@8	138 return (fVal == rd);
rlm@8	139 tagged WB_Store .st :
rlm@8	140 return False;
rlm@8	141 tagged WB_Host .x :
rlm@8	142 return False;
rlm@8	143 endcase
rlm@8	144 endfunction
rlm@8	145
rlm@8	146
rlm@8	147 //-----------------------------------------------------------
rlm@8	148 // Stall funct for wbQ
rlm@8	149 //-----------------------------------------------------------
rlm@8	150 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
rlm@8	151 case (inst) matches
rlm@8	152 // -- Memory Ops ------------------------------------------------
rlm@8	153 tagged LW .it :
rlm@8	154 return f.find(it.rbase);
rlm@8	155 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
rlm@8	156 return (f.find(addr) \|\| f.find2(dreg));
rlm@8	157
rlm@8	158 // -- Simple Ops ------------------------------------------------
rlm@8	159 tagged ADDIU .it : return f.find(it.rsrc);
rlm@8	160 tagged SLTI .it : return f.find(it.rsrc);
rlm@8	161 tagged SLTIU .it : return f.find(it.rsrc);
rlm@8	162 tagged ANDI .it : return f.find(it.rsrc);
rlm@8	163 tagged ORI .it : return f.find(it.rsrc);
rlm@8	164 tagged XORI .it : return f.find(it.rsrc);
rlm@8	165
rlm@8	166 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
rlm@8	167 tagged SLL .it : return f.find(it.rsrc);
rlm@8	168 tagged SRL .it : return f.find(it.rsrc);
rlm@8	169 tagged SRA .it : return f.find(it.rsrc);
rlm@8	170 tagged SLLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	171 tagged SRLV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	172 tagged SRAV .it : return (f.find(it.rsrc) \|\| f.find(it.rshamt));
rlm@8	173 tagged ADDU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	174 tagged SUBU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	175 tagged AND .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	176 tagged OR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	177 tagged XOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	178 tagged NOR .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	179 tagged SLT .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	180 tagged SLTU .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	181
rlm@8	182
rlm@8	183 // -- Branches --------------------------------------------------
rlm@8	184
rlm@8	185 tagged BLEZ .it : return (f.find(it.rsrc));
rlm@8	186 tagged BGTZ .it : return (f.find(it.rsrc));
rlm@8	187 tagged BLTZ .it : return (f.find(it.rsrc));
rlm@8	188 tagged BGEZ .it : return (f.find(it.rsrc));
rlm@8	189 tagged BEQ .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	190 tagged BNE .it : return (f.find(it.rsrc1) \|\| f.find2(it.rsrc2));
rlm@8	191
rlm@8	192 // -- Jumps -----------------------------------------------------
rlm@8	193
rlm@8	194 tagged J .it : return False;
rlm@8	195 tagged JR .it : return f.find(it.rsrc);
rlm@8	196 tagged JALR .it : return f.find(it.rsrc);
rlm@8	197 tagged JAL .it : return False;
rlm@8	198
rlm@8	199 // -- Cop0 ------------------------------------------------------
rlm@8	200
rlm@8	201 tagged MTC0 .it : return f.find(it.rsrc);
rlm@8	202 tagged MFC0 .it : return False;
rlm@8	203
rlm@8	204 // -- Illegal ---------------------------------------------------
rlm@8	205
rlm@8	206 default : return False;
rlm@8	207
rlm@8	208 endcase
rlm@8	209 endfunction
rlm@8	210 //-----------------------------------------------------------
rlm@8	211 // Reference processor
rlm@8	212 //-----------------------------------------------------------
rlm@8	213
rlm@8	214
rlm@8	215 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
rlm@8	216 //(* synthesize *)
rlm@8	217
punk@51	218 module mkProc( Proc );
rlm@8	219
rlm@8	220 //-----------------------------------------------------------
rlm@8	221 // State
rlm@8	222
rlm@8	223 // Standard processor state
rlm@8	224
rlm@8	225 Reg#(Addr) pc <- mkReg(32'h00001000);
rlm@8	226 Reg#(Epoch) epoch <- mkReg(0);
rlm@8	227 Reg#(Stage) stage <- mkReg(PCgen);
rlm@8	228 BRFile rf <- mkBRFile;
rlm@8	229
rlm@8	230 // Branch Prediction
rlm@8	231 BranchPred bp <- mkBranchPred();
rlm@8	232 FIFO#(PCStat) execpc <- mkLFIFO();
rlm@8	233
rlm@8	234 // Pipelines
rlm@8	235 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
rlm@8	236 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
rlm@8	237
punk@33	238 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
rlm@8	239 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
rlm@8	240 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
rlm@8	241 Reg#(Bool) cp0_statsEn <- mkReg(False);
punk@33	242 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
punk@33	243 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
punk@33	244
rlm@8	245 // Memory request/response state
rlm@8	246
rlm@8	247 FIFO#(InstReq) instReqQ <- mkBFIFO1();
rlm@8	248 FIFO#(InstResp) instRespQ <- mkFIFO();
rlm@8	249
rlm@8	250 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
rlm@8	251 FIFO#(DataResp) dataRespQ <- mkFIFO();
rlm@8	252
punk@11	253 // Audio I/O
punk@43	254 FIFO#(AudioProcessorUnit) inAudioFifo <- mkSizedFIFO(512);
punk@11	255 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
punk@11	256
punk@11	257
punk@11	258 // Statistics state (2010)
rlm@35	259 // Reg#(Stat) num_cycles <- mkReg(0);
rlm@35	260 // Reg#(Stat) num_inst <- mkReg(0);
rlm@8	261
rlm@8	262 //Or:
punk@11	263 // Statistics state
rlm@49	264
rlm@49	265 //rlm: removing these to avoid their broken stupidness.
rlm@49	266 //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
rlm@49	267 //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
rlm@8	268
rlm@8	269 //-----------------------------------------------------------
rlm@8	270 // Rules
rlm@8	271
rlm@8	272 (* descending_urgency = "exec, pcgen" *)
rlm@8	273 rule pcgen; //( stage == PCgen );
rlm@8	274 let pc_plus4 = pc + 4;
rlm@8	275
rlm@8	276 traceTiny("mkProc", "pc",pc);
rlm@8	277 traceTiny("mkProc", "pcgen","P");
rlm@8	278 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
rlm@8	279
rlm@8	280 let next_pc = bp.get(pc);
rlm@8	281 if (next_pc matches tagged Valid .npc)
rlm@8	282 begin
rlm@8	283 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
rlm@8	284 pc <= npc;
rlm@8	285 end
rlm@8	286 else
rlm@8	287 begin
rlm@8	288 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
rlm@8	289 pc <= pc_plus4;
rlm@8	290 end
rlm@8	291
rlm@8	292 endrule
rlm@8	293
rlm@8	294 rule discard (instRespQ.first() matches tagged LoadResp .ld
rlm@8	295 &&& ld.tag != epoch);
rlm@8	296 traceTiny("mkProc", "stage", "D");
rlm@8	297 instRespQ.deq();
rlm@8	298 endrule
rlm@8	299
rlm@8	300 (* conflict_free = "exec, writeback" *)
rlm@8	301 rule exec (instRespQ.first() matches tagged LoadResp.ld
rlm@8	302 &&& (ld.tag == epoch)
rlm@8	303 &&& unpack(ld.data) matches .inst
rlm@8	304 &&& !stall(inst, wbQ));
rlm@8	305
rlm@8	306 // Some abbreviations
rlm@8	307 let sext = signExtend;
rlm@8	308 let zext = zeroExtend;
rlm@8	309 let sra = signedShiftRight;
rlm@8	310
rlm@8	311 // Get the instruction
rlm@8	312
rlm@8	313 instRespQ.deq();
rlm@8	314 Instr inst
rlm@8	315 = case ( instRespQ.first() ) matches
rlm@8	316 tagged LoadResp .ld : return unpack(ld.data);
rlm@8	317 tagged StoreResp .st : return ?;
rlm@8	318 endcase;
rlm@8	319
rlm@8	320 // Get the PC info
rlm@8	321 let instrpc = pcQ.first().qpc;
rlm@8	322 let pc_plus4 = instrpc + 4;
rlm@8	323
rlm@8	324 Bool branchTaken = False;
rlm@8	325 Addr newPC = pc_plus4;
rlm@8	326
rlm@8	327 // Tracing
rlm@8	328 traceTiny("mkProc", "exec","X");
rlm@8	329 traceTiny("mkProc", "exInstTiny",inst);
rlm@8	330 traceFull("mkProc", "exInstFull",inst);
rlm@8	331
rlm@8	332 case ( inst ) matches
rlm@8	333
rlm@8	334 // -- Memory Ops ------------------------------------------------
rlm@8	335
rlm@8	336 tagged LW .it :
rlm@8	337 begin
rlm@8	338 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	339 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
rlm@8	340 wbQ.enq(tagged WB_Load it.rdst);
rlm@8	341 end
rlm@8	342
rlm@8	343 tagged SW .it :
rlm@8	344 begin
rlm@8	345 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8	346 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
rlm@8	347 wbQ.enq(tagged WB_Store);
rlm@8	348 end
rlm@8	349
rlm@8	350 // -- Simple Ops ------------------------------------------------
rlm@8	351
rlm@8	352 tagged ADDIU .it :
rlm@8	353 begin
rlm@8	354 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
rlm@8	355 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
rlm@8	356 end
rlm@8	357 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
rlm@8	358 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
rlm@8	359 tagged ANDI .it :
rlm@8	360 begin
rlm@8	361 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	362 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
rlm@8	363 end
rlm@8	364 tagged ORI .it :
rlm@8	365 begin
rlm@8	366 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	367 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) \| zext_it_imm)} );
rlm@8	368 end
rlm@8	369 tagged XORI .it :
rlm@8	370 begin
rlm@8	371 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	372 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
rlm@8	373 end
rlm@8	374 tagged LUI .it :
rlm@8	375 begin
rlm@8	376 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8	377 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
rlm@8	378 end
rlm@8	379
rlm@8	380 tagged SLL .it :
rlm@8	381 begin
rlm@8	382 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	383 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
rlm@8	384 end
rlm@8	385 tagged SRL .it :
rlm@8	386 begin
rlm@8	387 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	388 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
rlm@8	389 end
rlm@8	390 tagged SRA .it :
rlm@8	391 begin
rlm@8	392 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8	393 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
rlm@8	394 end
rlm@8	395 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
rlm@8	396 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
rlm@8	397 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
rlm@8	398 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
rlm@8	399 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
rlm@8	400 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
rlm@8	401 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2) )} );
rlm@8	402 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
rlm@8	403 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) \| rf.rd2(it.rsrc2)) )} );
rlm@8	404 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	405 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8	406
rlm@8	407 // -- Branches --------------------------------------------------
rlm@8	408
rlm@8	409 tagged BLEZ .it :
rlm@8	410 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
rlm@8	411 begin
rlm@8	412 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	413 branchTaken = True;
rlm@8	414 end
rlm@8	415
rlm@8	416 tagged BGTZ .it :
rlm@8	417 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
rlm@8	418 begin
rlm@8	419 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	420 branchTaken = True;
rlm@8	421 end
rlm@8	422
rlm@8	423 tagged BLTZ .it :
rlm@8	424 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
rlm@8	425 begin
rlm@8	426 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	427 branchTaken = True;
rlm@8	428 end
rlm@8	429
rlm@8	430 tagged BGEZ .it :
rlm@8	431 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
rlm@8	432 begin
rlm@8	433 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	434 branchTaken = True;
rlm@8	435 end
rlm@8	436
rlm@8	437 tagged BEQ .it :
rlm@8	438 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
rlm@8	439 begin
rlm@8	440 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	441 branchTaken = True;
rlm@8	442 end
rlm@8	443
rlm@8	444 tagged BNE .it :
rlm@8	445 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
rlm@8	446 begin
rlm@8	447 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8	448 branchTaken = True;
rlm@8	449 end
rlm@8	450
rlm@8	451 // -- Jumps -----------------------------------------------------
rlm@8	452
rlm@8	453 tagged J .it :
rlm@8	454 begin
rlm@8	455 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	456 branchTaken = True;
rlm@8	457 end
rlm@8	458
rlm@8	459 tagged JR .it :
punk@42	460 begin
rlm@8	461 newPC = rf.rd1(it.rsrc);
rlm@8	462 branchTaken = True;
rlm@8	463 end
rlm@8	464
rlm@8	465 tagged JAL .it :
rlm@8	466 begin
rlm@8	467 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
rlm@8	468 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8	469 branchTaken = True;
rlm@8	470 end
rlm@8	471
rlm@8	472 tagged JALR .it :
rlm@8	473 begin
rlm@8	474 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
rlm@8	475 newPC = rf.rd1(it.rsrc);
rlm@8	476 branchTaken = True;
rlm@8	477 end
rlm@8	478
rlm@8	479 // -- Cop0 ------------------------------------------------------
rlm@8	480
punk@33	481 tagged MTC0 .it : //Recieve things from host computer
rlm@8	482 begin
punk@43	483 // $display( " PROCESSOR MTC0 call\n");
rlm@8	484 case ( it.cop0dst )
rlm@8	485 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
rlm@8	486 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
punk@33	487 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
punk@33	488 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32
rlm@8	489 default :
rlm@8	490 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
rlm@8	491 endcase
rlm@8	492 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
rlm@8	493 end
rlm@8	494
rlm@8	495 //this is host stuff?
punk@33	496 tagged MFC0 .it : //Things out
rlm@8	497 begin
rlm@8	498 case ( it.cop0src )
rlm@8	499 // not actually an ALU instruction but don't have the format otherwise
rlm@8	500 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
rlm@8	501 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
rlm@8	502 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
punk@33	503 5'd25 : begin
punk@53	504 // $display( "**** EOF Requested\n ");
punk@50	505 let sample = inAudioFifo.first();
punk@50	506 case (sample) matches
punk@50	507 tagged EndOfFile :
punk@50	508 begin
punk@50	509 $display("PROCESSOR sent toC EOF");
punk@50	510 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(True)) }); // Reading clears bit
punk@50	511 inAudioFifo.deq;
punk@50	512 end
punk@50	513 tagged Sample .data:
punk@50	514 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(False)) }); // Reading clears bit
punk@50	515 endcase
punk@33	516 end
punk@33	517 5'd28 : begin
punk@53	518 // $display( "***** Reqesting Sample \n");
punk@33	519 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
punk@33	520 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
punk@43	521 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
punk@33	522 else $display ( "Audio File EOF Reached. Invalid sample request.");
punk@33	523 inAudioFifo.deq();
punk@33	524 end
rlm@8	525 default :
rlm@8	526 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
rlm@8	527 endcase
rlm@8	528 end
rlm@8	529
rlm@8	530 // -- Illegal ---------------------------------------------------
rlm@8	531
rlm@8	532 default :
rlm@8	533 $display( " RTL-ERROR : %m : Illegal instruction !" );
rlm@8	534
rlm@8	535 endcase
rlm@8	536
rlm@8	537 //evaluate branch prediction
rlm@8	538 Addr ppc = pcQ.first().qnxtpc; //predicted branch
rlm@8	539 if (ppc != newPC) //prediction wrong
rlm@8	540 begin
rlm@8	541 epoch <= pcQ.first().qepoch + 1;
rlm@8	542 bp.upd(instrpc, newPC); //update branch predictor
rlm@8	543 pcQ.clear();
rlm@8	544 pc <= newPC;
rlm@8	545 end
rlm@8	546 else
rlm@8	547 pcQ.deq();
rlm@49	548 //rlm: removing
rlm@49	549 // if ( cp0_statsEn )
rlm@49	550 // num_inst.incr();
rlm@8	551
rlm@8	552 endrule
rlm@8	553
rlm@8	554 rule writeback; // ( stage == Writeback );
rlm@8	555 traceTiny("mkProc", "writeback","W");
rlm@8	556
rlm@8	557
rlm@8	558 // get what to do off the writeback queue
rlm@8	559 wbQ.deq();
rlm@8	560 case (wbQ.first()) matches
rlm@8	561 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
rlm@8	562 tagged WB_Load .regWr :
rlm@8	563 begin
rlm@8	564 dataRespQ.deq();
rlm@8	565 if (dataRespQ.first() matches tagged LoadResp .ld)
rlm@8	566 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
rlm@8	567 end
rlm@8	568 tagged WB_Store : dataRespQ.deq();
rlm@8	569 tagged WB_Host .dat : noAction;
rlm@8	570 endcase
rlm@8	571
rlm@8	572 endrule
rlm@8	573
rlm@49	574 //rlm remove
rlm@49	575 // rule inc_num_cycles;
rlm@49	576 // if ( cp0_statsEn )
rlm@49	577 // num_cycles.incr();
rlm@49	578 // endrule
punk@11	579
punk@43	580 /*
punk@11	581 // for now, we don't do anything.
punk@43	582 rule connectAudioReqResp;
punk@43	583 $display("rlm: PROCESSOR copies a datum\n");
punk@43	584 outAudioFifo.enq(inAudioFifo.first());
punk@43	585 inAudioFifo.deq;
punk@43	586 endrule
punk@43	587 */
punk@50	588 /*
punk@33	589 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
punk@37	590 $display (" PROCESSOR End Audio Flag Set ");
punk@33	591 cp0_audioEOF <= True;
punk@33	592 inAudioFifo.deq;
punk@33	593 endrule
punk@50	594 */
punk@50	595 rule sendProcEnd (cp0_progComp);
punk@33	596 $display (" PROCESSOR Says Program Complete ");
punk@33	597 outAudioFifo.enq(tagged EndOfFile);
punk@33	598 cp0_progComp <= False; //only send one. And functions to reset
punk@11	599 endrule
punk@43	600
punk@12	601
rlm@8	602 //-----------------------------------------------------------
rlm@8	603 // Methods
rlm@8	604
rlm@8	605 interface Client imem_client;
punk@21	606 interface Get request = fifoToGet(instReqQ);
punk@21	607 interface Put response = fifoToPut(instRespQ);
rlm@8	608 endinterface
rlm@8	609
rlm@8	610 interface Client dmem_client;
punk@21	611 interface Get request = fifoToGet(dataReqQ);
punk@21	612 interface Put response = fifoToPut(dataRespQ);
rlm@8	613 endinterface
rlm@8	614
rlm@8	615 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
rlm@8	616
punk@36	617 /*
punk@36	618 interface CPUToHost tohost;
punk@36	619 method Bit#(32) cpuToHost(int req);
punk@36	620 return (case (req)
punk@36	621 0: cp0_tohost;
punk@36	622 1: pc;
punk@36	623 2: zeroExtend(pack(stage));
punk@36	624 endcase);
punk@36	625 endmethod
punk@36	626 endinterface
punk@36	627 */
punk@36	628
punk@21	629 interface Get sampleOutput = fifoToGet(outAudioFifo);
punk@36	630 interface Put sampleInput = fifoToPut(inAudioFifo);
punk@11	631
rlm@8	632 endmodule
rlm@8	633

Mercurial > pygar

annotate modules/bluespec/Pygar/core/Processor.bsv @ 53:2991344775f8 pygar svn.54