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1
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2 import Trace::*;
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3
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4 //----------------------------------------------------------------------
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5 // Other typedefs
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6 //----------------------------------------------------------------------
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7
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8 typedef Bit#(32) Addr;
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9 typedef Int#(18) Stat;
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10
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11 //----------------------------------------------------------------------
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12 // Basic instruction type
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13 //----------------------------------------------------------------------
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14
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15 typedef Bit#(5) Rindx;
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16 typedef Bit#(16) Simm;
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17 typedef Bit#(16) Zimm;
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18 typedef Bit#(8) Epoch;
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19 typedef Bit#(5) Shamt;
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20 typedef Bit#(26) Target;
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21 typedef Bit#(5) CP0indx;
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22 typedef Bit#(32) Data;
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23
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24 typedef enum
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25 {
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26 Taken,
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27 NotTaken
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28 }
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29 Direction
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30 deriving(Bits,Eq);
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31
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32
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33 //----------------------------------------------------------------------
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34 // Pipeline typedefs
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35 //----------------------------------------------------------------------
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36
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37 typedef union tagged
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38 {
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39 Tuple2#(Rindx,Data) ALUWB;
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40 Rindx MemWB;
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41 Tuple2#(Rindx,Data) CoWB;
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42 }
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43 WritebackType
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44 deriving(Bits,Eq);
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45
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46 ////////////////////////
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47 // I Add Writeback queue type
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48 ////////////
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49 typedef union tagged
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50 {
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51 struct {Bit#(32) data; Rindx dest; } WB_ALU;
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52 Bit#(32) WB_Host;
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53 Rindx WB_Load;
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54 void WB_Store;
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55 }
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56 WBResult deriving(Eq, Bits);
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57
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58 typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
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59 //typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
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60
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61 typedef union tagged
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62 {
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63
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64 struct { Rindx rbase; Rindx rdst; Simm offset; } LW;
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65 struct { Rindx rbase; Rindx rsrc; Simm offset; } SW;
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66
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67 struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU;
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68 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI;
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69 struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU;
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70 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI;
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71 struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI;
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72 struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI;
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73 struct { Rindx rdst; Zimm imm; } LUI;
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74
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75 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL;
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76 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL;
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77 struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA;
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78 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV;
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79 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV;
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80 struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV;
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81 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU;
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82 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU;
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83 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND;
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84 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR;
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85 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR;
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86 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR;
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87 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT;
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88 struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU;
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89
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90 struct { Target target; } J;
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91 struct { Target target; } JAL;
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92 struct { Rindx rsrc; } JR;
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93 struct { Rindx rsrc; Rindx rdst; } JALR;
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94 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ;
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95 struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE;
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96 struct { Rindx rsrc; Simm offset; } BLEZ;
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97 struct { Rindx rsrc; Simm offset; } BGTZ;
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98 struct { Rindx rsrc; Simm offset; } BLTZ;
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99 struct { Rindx rsrc; Simm offset; } BGEZ;
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100
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101 struct { Rindx rdst; CP0indx cop0src; } MFC0;
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102 struct { Rindx rsrc; CP0indx cop0dst; } MTC0;
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103
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104 void ILLEGAL;
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105
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106 }
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107 Instr deriving(Eq);
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108
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109 //----------------------------------------------------------------------
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rlm@8
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110 // Pack and Unpack
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111 //----------------------------------------------------------------------
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112
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113 Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000;
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114 Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010;
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115 Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011;
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116 Bit#(6) fcSLLV = 6'b000100;
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117 Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110;
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118 Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111;
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119 Bit#(6) fcADDU = 6'b100001;
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120 Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011;
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121 Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100;
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122 Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101;
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123 Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110;
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124 Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111;
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125 Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010;
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126 Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011;
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127
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128 Bit#(6) opJ = 6'b000010;
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129 Bit#(6) opJAL = 6'b000011;
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130 Bit#(6) fcJR = 6'b001000;
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131 Bit#(6) fcJALR = 6'b001001;
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132 Bit#(6) opBEQ = 6'b000100;
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133 Bit#(6) opBNE = 6'b000101;
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134 Bit#(6) opBLEZ = 6'b000110;
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135 Bit#(6) opBGTZ = 6'b000111;
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136 Bit#(5) rtBLTZ = 5'b00000;
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137 Bit#(5) rtBGEZ = 5'b00001;
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138
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139 Bit#(5) rsMFC0 = 5'b00000;
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140 Bit#(5) rsMTC0 = 5'b00100;
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141
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142 instance Bits#(Instr,32);
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143
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144 // Pack Function
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145
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146 function Bit#(32) pack( Instr instr );
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147
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148 case ( instr ) matches
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149
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150 tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset };
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151 tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset };
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152
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153 tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm };
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154 tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm };
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155 tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm };
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156 tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm };
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157 tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm };
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158 tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm };
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159 tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm };
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160
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161 tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL };
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162 tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL };
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163 tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA };
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164
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165 tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV };
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166 tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV };
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167 tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV };
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168
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169 tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU };
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170 tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU };
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171 tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND };
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172 tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR };
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173 tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR };
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174 tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR };
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175 tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT };
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176 tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU };
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177
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178 tagged J .it : return { opJ, it.target };
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179 tagged JAL .it : return { opJAL, it.target };
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180 tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR };
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181 tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR };
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182 tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset };
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183 tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset };
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184 tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset };
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185 tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset };
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186 tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset };
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187 tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset };
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188
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189 tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 };
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190 tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 };
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191
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192 endcase
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193
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194 endfunction
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195
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196 // Unpack Function
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197
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198 function Instr unpack( Bit#(32) instrBits );
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199
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200 let opcode = instrBits[ 31 : 26 ];
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201 let rs = instrBits[ 25 : 21 ];
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202 let rt = instrBits[ 20 : 16 ];
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rlm@8
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203 let rd = instrBits[ 15 : 11 ];
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204 let shamt = instrBits[ 10 : 6 ];
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rlm@8
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205 let funct = instrBits[ 5 : 0 ];
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206 let imm = instrBits[ 15 : 0 ];
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207 let target = instrBits[ 25 : 0 ];
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208
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209 case ( opcode )
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210
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211 opLW : return LW { rbase:rs, rdst:rt, offset:imm };
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212 opSW : return SW { rbase:rs, rsrc:rt, offset:imm };
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213 opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm };
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214 opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm };
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rlm@8
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215 opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm };
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216 opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm };
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217 opORI : return ORI { rsrc:rs, rdst:rt, imm:imm };
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rlm@8
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218 opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm };
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rlm@8
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219 opLUI : return LUI { rdst:rt, imm:imm };
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rlm@8
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220 opJ : return J { target:target };
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rlm@8
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221 opJAL : return JAL { target:target };
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rlm@8
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222 opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm };
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rlm@8
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223 opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm };
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rlm@8
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224 opBLEZ : return BLEZ { rsrc:rs, offset:imm };
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225 opBGTZ : return BGTZ { rsrc:rs, offset:imm };
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226
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227 opFUNC :
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rlm@8
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228 case ( funct )
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rlm@8
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229 fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt };
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rlm@8
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230 fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt };
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rlm@8
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231 fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt };
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rlm@8
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232 fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs };
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rlm@8
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233 fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs };
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rlm@8
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234 fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs };
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rlm@8
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235 fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd };
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rlm@8
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236 fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd };
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rlm@8
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237 fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd };
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rlm@8
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238 fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd };
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rlm@8
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239 fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd };
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rlm@8
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240 fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd };
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rlm@8
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241 fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd };
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rlm@8
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242 fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd };
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rlm@8
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243 fcJR : return JR { rsrc:rs };
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rlm@8
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244 fcJALR : return JALR { rsrc:rs, rdst:rd };
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rlm@8
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245 default : return ILLEGAL;
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rlm@8
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246 endcase
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247
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rlm@8
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248 opRT :
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rlm@8
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249 case ( rt )
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rlm@8
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250 rtBLTZ : return BLTZ { rsrc:rs, offset:imm };
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rlm@8
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251 rtBGEZ : return BGEZ { rsrc:rs, offset:imm };
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rlm@8
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252 default : return ILLEGAL;
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rlm@8
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253 endcase
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rlm@8
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254
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rlm@8
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255 opRS :
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rlm@8
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256 case ( rs )
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rlm@8
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257 rsMFC0 : return MFC0 { rdst:rt, cop0src:rd };
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rlm@8
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258 rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd };
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rlm@8
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259 default : return ILLEGAL;
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rlm@8
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260 endcase
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rlm@8
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261
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rlm@8
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262 default : return ILLEGAL;
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rlm@8
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263
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rlm@8
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264 endcase
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rlm@8
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265
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rlm@8
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266 endfunction
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rlm@8
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267
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rlm@8
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268 endinstance
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rlm@8
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269
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rlm@8
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270 //----------------------------------------------------------------------
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rlm@8
|
271 // Trace
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|
rlm@8
|
272 //----------------------------------------------------------------------
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rlm@8
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273
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rlm@8
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274 instance Traceable#(Instr);
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rlm@8
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275
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rlm@8
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276 function Action traceTiny( String loc, String ttag, Instr inst );
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rlm@8
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277 case ( inst ) matches
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rlm@8
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278
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rlm@8
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279 tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag );
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rlm@8
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280 tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag );
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rlm@8
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281
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rlm@8
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282 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag );
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rlm@8
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283 tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag );
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rlm@8
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284 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag );
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rlm@8
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285 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag );
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rlm@8
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286 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag );
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rlm@8
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287 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag );
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rlm@8
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288 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag );
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rlm@8
|
289
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rlm@8
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290 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag );
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rlm@8
|
291 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag );
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rlm@8
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292 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag );
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rlm@8
|
293 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag );
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rlm@8
|
294 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag );
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rlm@8
|
295 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag );
|
|
rlm@8
|
296
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rlm@8
|
297 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag );
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rlm@8
|
298 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag );
|
|
rlm@8
|
299 tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag );
|
|
rlm@8
|
300 tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag );
|
|
rlm@8
|
301 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag );
|
|
rlm@8
|
302 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag );
|
|
rlm@8
|
303 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag );
|
|
rlm@8
|
304 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag );
|
|
rlm@8
|
305
|
|
rlm@8
|
306 tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag );
|
|
rlm@8
|
307 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag );
|
|
rlm@8
|
308 tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag );
|
|
rlm@8
|
309 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag );
|
|
rlm@8
|
310 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag );
|
|
rlm@8
|
311 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag );
|
|
rlm@8
|
312 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag );
|
|
rlm@8
|
313 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag );
|
|
rlm@8
|
314 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag );
|
|
rlm@8
|
315 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag );
|
|
rlm@8
|
316
|
|
rlm@8
|
317 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag );
|
|
rlm@8
|
318 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag );
|
|
rlm@8
|
319
|
|
rlm@8
|
320 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag );
|
|
rlm@8
|
321
|
|
rlm@8
|
322 endcase
|
|
rlm@8
|
323 endfunction
|
|
rlm@8
|
324
|
|
rlm@8
|
325 function Action traceFull( String loc, String ttag, Instr inst );
|
|
rlm@8
|
326 case ( inst ) matches
|
|
rlm@8
|
327
|
|
rlm@8
|
328 tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase );
|
|
rlm@8
|
329 tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase );
|
|
rlm@8
|
330
|
|
rlm@8
|
331 tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
332 tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
333 tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
334 tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
335 tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
336 tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
|
|
rlm@8
|
337 tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm );
|
|
rlm@8
|
338
|
|
rlm@8
|
339 tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
|
|
rlm@8
|
340 tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
|
|
rlm@8
|
341 tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt );
|
|
rlm@8
|
342 tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
|
|
rlm@8
|
343 tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
|
|
rlm@8
|
344 tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
|
|
rlm@8
|
345
|
|
rlm@8
|
346 tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
347 tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
348 tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
349 tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
350 tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
351 tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
352 tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
353 tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
|
|
rlm@8
|
354
|
|
rlm@8
|
355 tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target );
|
|
rlm@8
|
356 tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target );
|
|
rlm@8
|
357 tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc );
|
|
rlm@8
|
358 tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc );
|
|
rlm@8
|
359 tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
|
|
rlm@8
|
360 tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
|
|
rlm@8
|
361 tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
|
|
rlm@8
|
362 tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
|
|
rlm@8
|
363 tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
|
|
rlm@8
|
364 tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
|
|
rlm@8
|
365
|
|
rlm@8
|
366 tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src );
|
|
rlm@8
|
367 tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst );
|
|
rlm@8
|
368
|
|
rlm@8
|
369 tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag );
|
|
rlm@8
|
370
|
|
rlm@8
|
371 endcase
|
|
rlm@8
|
372 endfunction
|
|
rlm@8
|
373
|
|
rlm@8
|
374 endinstance
|
|
rlm@8
|
375
|
