annotate modules/bluespec/Pygar/lab4/MemTypes.bsv @ 63:1d5cbb5343d2 pygar svn.64

[svn r64] mods to compile correctly for FPGA
author punk
date Mon, 10 May 2010 22:54:54 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 import Trace::*;
rlm@8 2
rlm@8 3 //----------------------------------------------------------------------
rlm@8 4 // Basic memory requests and responses
rlm@8 5 //----------------------------------------------------------------------
rlm@8 6
rlm@8 7 typedef union tagged
rlm@8 8 {
rlm@8 9 struct { Bit#(addrSz) addr; Bit#(tagSz) tag; } LoadReq;
rlm@8 10 struct { Bit#(addrSz) addr; Bit#(tagSz) tag; Bit#(dataSz) data; } StoreReq;
rlm@8 11 }
rlm@8 12 MemReq#( type addrSz, type tagSz, type dataSz )
rlm@8 13 deriving(Eq,Bits);
rlm@8 14
rlm@8 15 typedef union tagged
rlm@8 16 {
rlm@8 17 struct { Bit#(tagSz) tag; Bit#(dataSz) data; } LoadResp;
rlm@8 18 struct { Bit#(tagSz) tag; } StoreResp;
rlm@8 19 }
rlm@8 20 MemResp#( type tagSz, type dataSz )
rlm@8 21 deriving(Eq,Bits);
rlm@8 22
rlm@8 23 //----------------------------------------------------------------------
rlm@8 24 // Specialized req/resp for inst/data/host
rlm@8 25 //----------------------------------------------------------------------
rlm@8 26
rlm@8 27 typedef 32 AddrSz;
rlm@8 28 typedef 08 TagSz;
rlm@8 29 typedef 32 DataSz;
rlm@8 30 typedef 32 InstSz;
rlm@8 31 typedef 32 HostDataSz;
rlm@8 32
rlm@8 33 typedef MemReq#(AddrSz,TagSz,0) InstReq;
rlm@8 34 typedef MemResp#(TagSz,InstSz) InstResp;
rlm@8 35
rlm@8 36 typedef MemReq#(AddrSz,TagSz,DataSz) DataReq;
rlm@8 37 typedef MemResp#(TagSz,DataSz) DataResp;
rlm@8 38
rlm@8 39 typedef MemReq#(AddrSz,TagSz,HostDataSz) HostReq;
rlm@8 40 typedef MemResp#(TagSz,HostDataSz) HostResp;
rlm@8 41
rlm@8 42 //----------------------------------------------------------------------
rlm@8 43 // Specialized req/resp for main memory
rlm@8 44 //----------------------------------------------------------------------
rlm@8 45
rlm@8 46 typedef 32 MainMemAddrSz;
rlm@8 47 typedef 08 MainMemTagSz;
rlm@8 48 typedef 32 MainMemDataSz;
rlm@8 49
rlm@8 50 typedef MemReq#(MainMemAddrSz,MainMemTagSz,MainMemDataSz) MainMemReq;
rlm@8 51 typedef MemResp#(MainMemTagSz,MainMemDataSz) MainMemResp;
rlm@8 52
rlm@8 53 //----------------------------------------------------------------------
rlm@8 54 // Tracing Functions
rlm@8 55 //----------------------------------------------------------------------
rlm@8 56
rlm@8 57 instance Traceable#(MemReq#(a,b,c));
rlm@8 58
rlm@8 59 function Action traceTiny( String loc, String ttag, MemReq#(a,b,c) req );
rlm@8 60 case ( req ) matches
rlm@8 61 tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag );
rlm@8 62 tagged StoreReq .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag );
rlm@8 63 endcase
rlm@8 64 endfunction
rlm@8 65
rlm@8 66 function Action traceFull( String loc, String ttag, MemReq#(a,b,c) req );
rlm@8 67 case ( req ) matches
rlm@8 68 tagged LoadReq .ld : $fdisplay(stderr, " => %s:%s Ld { addr=%x, tag=%x }", loc, ttag, ld.addr, ld.tag );
rlm@8 69 tagged StoreReq .st : $fdisplay(stderr, " => %s:%s St { addr=%x, tag=%x, data=%x }", loc, ttag, st.addr, st.tag, st.data );
rlm@8 70 endcase
rlm@8 71 endfunction
rlm@8 72
rlm@8 73 endinstance
rlm@8 74
rlm@8 75 instance Traceable#(MemResp#(a,b));
rlm@8 76
rlm@8 77 function Action traceTiny( String loc, String ttag, MemResp#(a,b) resp );
rlm@8 78 case ( resp ) matches
rlm@8 79 tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s l%2x", loc, ttag, ld.tag );
rlm@8 80 tagged StoreResp .st : $fdisplay(stderr, " => %s:%s s%2x", loc, ttag, st.tag );
rlm@8 81 endcase
rlm@8 82 endfunction
rlm@8 83
rlm@8 84 function Action traceFull( String loc, String ttag, MemResp#(a,b) resp );
rlm@8 85 case ( resp ) matches
rlm@8 86 tagged LoadResp .ld : $fdisplay(stderr, " => %s:%s Ld { tag=%x, data=%x }", loc, ttag, ld.tag, ld.data );
rlm@8 87 tagged StoreResp .st : $fdisplay(stderr, " => %s:%s St { tag=%x }", loc, ttag, st.tag );
rlm@8 88 endcase
rlm@8 89 endfunction
rlm@8 90
rlm@8 91 endinstance
rlm@8 92