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annotate modules/bluespec/Pygar/core/Processor.bsv @ 67:0ede0715dbd6 pygar svn.68

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[svn r68] added sensible benchmarks
author rlm
date Tue, 11 May 2010 23:23:21 -0400
parents cf8bb3038cbd
children 44cc00df1168
rev   line source
punk@51 1 // The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@19 23
rlm@8 24 import Connectable::*;
rlm@8 25 import GetPut::*;
rlm@8 26 import ClientServer::*;
rlm@8 27 import RegFile::*;
rlm@8 28
rlm@8 29 import FIFO::*;
rlm@8 30 import FIFOF::*;
rlm@8 31 import SFIFO::*;
rlm@8 32 import RWire::*;
rlm@8 33
punk@11 34 import Trace::*;
rlm@8 35 import BFIFO::*;
rlm@8 36 import MemTypes::*;
rlm@8 37 import ProcTypes::*;
rlm@8 38 import BRegFile::*;
rlm@8 39 import BranchPred::*;
rlm@8 40 //import PathTypes::*; This is only there to force the debugging
rlm@8 41
rlm@8 42 //AWB includes
rlm@8 43 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8 44 `include "asim/provides/soft_connections.bsh"
rlm@8 45 `include "asim/provides/common_services.bsh"
rlm@8 46
rlm@8 47 // Local includes
punk@11 48 //`include "asim/provides/processor_library.bsh" (included above directly)
punk@36 49
rlm@8 50 `include "asim/provides/common_services.bsh"
punk@26 51 `include "asim/provides/processor_library.bsh"
rlm@8 52
punk@11 53 // Local includes. Look for the correspondingly named .awb files
punk@11 54 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@11 55 // to find the actual Bluespec files which are used to generate
punk@11 56 // these includes. These files are specific to this audio processing
punk@11 57 // pipeline
punk@11 58
punk@12 59 `include "asim/provides/audio_pipe_types.bsh"
rlm@8 60
punk@12 61 //interface CPUToHost;
punk@12 62 // method Bit#(32) cpuToHost(int req);
punk@12 63 //endinterface
rlm@8 64
rlm@8 65 interface Proc;
rlm@8 66
rlm@8 67 // Interface from processor to caches
rlm@8 68 interface Client#(DataReq,DataResp) dmem_client;
rlm@8 69 interface Client#(InstReq,InstResp) imem_client;
rlm@8 70
rlm@8 71 // Interface for enabling/disabling statistics on the rest of the core
rlm@8 72 interface Get#(Bool) statsEn_get;
rlm@8 73
punk@12 74 // // Interface to host
punk@12 75 // interface CPUToHost tohost;
rlm@8 76
punk@11 77 // Interface to Audio Pipeline
punk@15 78 interface Get#(AudioProcessorUnit) sampleOutput;
punk@36 79 interface Put#(AudioProcessorUnit) sampleInput;
punk@11 80
rlm@8 81 endinterface
rlm@8 82
rlm@8 83 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
rlm@8 84
rlm@8 85 //-----------------------------------------------------------
rlm@8 86 // Helper functions
rlm@8 87 //-----------------------------------------------------------
rlm@8 88
rlm@8 89 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
rlm@8 90 return zeroExtend( pack( signedLT(val1,val2) ) );
rlm@8 91 endfunction
rlm@8 92
rlm@8 93 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
rlm@8 94 return zeroExtend( pack( val1 < val2 ) );
rlm@8 95 endfunction
rlm@8 96
rlm@8 97 function Bit#(32) rshft( Bit#(32) val );
rlm@8 98 return zeroExtend(val[4:0]);
rlm@8 99 endfunction
rlm@8 100
rlm@8 101
rlm@8 102 //-----------------------------------------------------------
rlm@8 103 // Find funct for wbQ
rlm@8 104 //-----------------------------------------------------------
rlm@8 105 function Bool findwbf(Rindx fVal, WBResult cmpVal);
rlm@8 106 case (cmpVal) matches
rlm@8 107 tagged WB_ALU {data:.res, dest:.rd} :
rlm@8 108 return (fVal == rd);
rlm@8 109 tagged WB_Load .rd :
rlm@8 110 return (fVal == rd);
rlm@8 111 tagged WB_Store .st :
rlm@8 112 return False;
rlm@8 113 tagged WB_Host .x :
rlm@8 114 return False;
rlm@8 115 endcase
rlm@8 116 endfunction
rlm@8 117
rlm@8 118
rlm@8 119 //-----------------------------------------------------------
rlm@8 120 // Stall funct for wbQ
rlm@8 121 //-----------------------------------------------------------
rlm@8 122 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
rlm@8 123 case (inst) matches
rlm@8 124 // -- Memory Ops ------------------------------------------------
rlm@8 125 tagged LW .it :
rlm@8 126 return f.find(it.rbase);
rlm@8 127 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
rlm@8 128 return (f.find(addr) || f.find2(dreg));
rlm@8 129
rlm@8 130 // -- Simple Ops ------------------------------------------------
rlm@8 131 tagged ADDIU .it : return f.find(it.rsrc);
rlm@8 132 tagged SLTI .it : return f.find(it.rsrc);
rlm@8 133 tagged SLTIU .it : return f.find(it.rsrc);
rlm@8 134 tagged ANDI .it : return f.find(it.rsrc);
rlm@8 135 tagged ORI .it : return f.find(it.rsrc);
rlm@8 136 tagged XORI .it : return f.find(it.rsrc);
rlm@8 137
rlm@8 138 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
rlm@8 139 tagged SLL .it : return f.find(it.rsrc);
rlm@8 140 tagged SRL .it : return f.find(it.rsrc);
rlm@8 141 tagged SRA .it : return f.find(it.rsrc);
rlm@8 142 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 143 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 144 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 145 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 146 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 147 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 148 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 149 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 150 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 151 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 152 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 153
rlm@8 154
rlm@8 155 // -- Branches --------------------------------------------------
rlm@8 156
rlm@8 157 tagged BLEZ .it : return (f.find(it.rsrc));
rlm@8 158 tagged BGTZ .it : return (f.find(it.rsrc));
rlm@8 159 tagged BLTZ .it : return (f.find(it.rsrc));
rlm@8 160 tagged BGEZ .it : return (f.find(it.rsrc));
rlm@8 161 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 162 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 163
rlm@8 164 // -- Jumps -----------------------------------------------------
rlm@8 165
rlm@8 166 tagged J .it : return False;
rlm@8 167 tagged JR .it : return f.find(it.rsrc);
rlm@8 168 tagged JALR .it : return f.find(it.rsrc);
rlm@8 169 tagged JAL .it : return False;
rlm@8 170
rlm@8 171 // -- Cop0 ------------------------------------------------------
rlm@8 172
rlm@8 173 tagged MTC0 .it : return f.find(it.rsrc);
rlm@8 174 tagged MFC0 .it : return False;
rlm@8 175
rlm@8 176 // -- Illegal ---------------------------------------------------
rlm@8 177
rlm@8 178 default : return False;
rlm@8 179
rlm@8 180 endcase
rlm@8 181 endfunction
rlm@8 182 //-----------------------------------------------------------
rlm@8 183 // Reference processor
rlm@8 184 //-----------------------------------------------------------
rlm@8 185
rlm@8 186
rlm@8 187 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
rlm@8 188 //(* synthesize *)
rlm@8 189
punk@51 190 module mkProc( Proc );
rlm@8 191
rlm@8 192 //-----------------------------------------------------------
rlm@8 193 // State
rlm@8 194
rlm@8 195 // Standard processor state
rlm@8 196
rlm@8 197 Reg#(Addr) pc <- mkReg(32'h00001000);
rlm@8 198 Reg#(Epoch) epoch <- mkReg(0);
rlm@8 199 Reg#(Stage) stage <- mkReg(PCgen);
punk@63 200 BRegFile rf <- mkBRegFile;
rlm@8 201
rlm@8 202 // Branch Prediction
rlm@8 203 BranchPred bp <- mkBranchPred();
rlm@8 204 FIFO#(PCStat) execpc <- mkLFIFO();
rlm@8 205
rlm@8 206 // Pipelines
rlm@8 207 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
rlm@8 208 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
rlm@8 209
punk@33 210 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
rlm@8 211 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
rlm@8 212 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
rlm@8 213 Reg#(Bool) cp0_statsEn <- mkReg(False);
punk@33 214 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
punk@33 215 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
punk@33 216
rlm@8 217 // Memory request/response state
rlm@8 218
rlm@8 219 FIFO#(InstReq) instReqQ <- mkBFIFO1();
rlm@8 220 FIFO#(InstResp) instRespQ <- mkFIFO();
rlm@8 221
rlm@8 222 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
rlm@8 223 FIFO#(DataResp) dataRespQ <- mkFIFO();
rlm@8 224
punk@11 225 // Audio I/O
punk@43 226 FIFO#(AudioProcessorUnit) inAudioFifo <- mkSizedFIFO(512);
punk@11 227 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
punk@11 228
punk@11 229
punk@11 230 // Statistics state (2010)
rlm@35 231 // Reg#(Stat) num_cycles <- mkReg(0);
rlm@35 232 // Reg#(Stat) num_inst <- mkReg(0);
rlm@8 233
rlm@8 234 //Or:
punk@11 235 // Statistics state
rlm@49 236
rlm@49 237 //rlm: removing these to avoid their broken stupidness.
rlm@49 238 //STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
rlm@49 239 //STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
rlm@8 240
rlm@8 241 //-----------------------------------------------------------
rlm@8 242 // Rules
rlm@8 243
rlm@8 244 (* descending_urgency = "exec, pcgen" *)
rlm@8 245 rule pcgen; //( stage == PCgen );
rlm@8 246 let pc_plus4 = pc + 4;
rlm@8 247
rlm@8 248 traceTiny("mkProc", "pc",pc);
rlm@8 249 traceTiny("mkProc", "pcgen","P");
rlm@8 250 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
rlm@8 251
rlm@8 252 let next_pc = bp.get(pc);
rlm@8 253 if (next_pc matches tagged Valid .npc)
rlm@8 254 begin
rlm@8 255 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
rlm@8 256 pc <= npc;
rlm@8 257 end
rlm@8 258 else
rlm@8 259 begin
rlm@8 260 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
rlm@8 261 pc <= pc_plus4;
rlm@8 262 end
rlm@8 263
rlm@8 264 endrule
rlm@8 265
rlm@8 266 rule discard (instRespQ.first() matches tagged LoadResp .ld
rlm@8 267 &&& ld.tag != epoch);
rlm@8 268 traceTiny("mkProc", "stage", "D");
rlm@8 269 instRespQ.deq();
rlm@8 270 endrule
rlm@8 271
rlm@8 272 (* conflict_free = "exec, writeback" *)
rlm@8 273 rule exec (instRespQ.first() matches tagged LoadResp.ld
rlm@8 274 &&& (ld.tag == epoch)
rlm@8 275 &&& unpack(ld.data) matches .inst
rlm@8 276 &&& !stall(inst, wbQ));
rlm@8 277
rlm@8 278 // Some abbreviations
rlm@8 279 let sext = signExtend;
rlm@8 280 let zext = zeroExtend;
rlm@8 281 let sra = signedShiftRight;
rlm@8 282
rlm@8 283 // Get the instruction
rlm@8 284
rlm@8 285 instRespQ.deq();
rlm@8 286 Instr inst
rlm@8 287 = case ( instRespQ.first() ) matches
rlm@8 288 tagged LoadResp .ld : return unpack(ld.data);
rlm@8 289 tagged StoreResp .st : return ?;
rlm@8 290 endcase;
rlm@8 291
rlm@8 292 // Get the PC info
rlm@8 293 let instrpc = pcQ.first().qpc;
rlm@8 294 let pc_plus4 = instrpc + 4;
rlm@8 295
rlm@8 296 Bool branchTaken = False;
rlm@8 297 Addr newPC = pc_plus4;
rlm@8 298
rlm@8 299 // Tracing
rlm@8 300 traceTiny("mkProc", "exec","X");
rlm@8 301 traceTiny("mkProc", "exInstTiny",inst);
rlm@8 302 traceFull("mkProc", "exInstFull",inst);
rlm@8 303
rlm@8 304 case ( inst ) matches
rlm@8 305
rlm@8 306 // -- Memory Ops ------------------------------------------------
rlm@8 307
rlm@8 308 tagged LW .it :
rlm@8 309 begin
punk@63 310 let val_rbase <- rf.rd1(it.rbase);
punk@63 311 Addr addr = val_rbase + sext(it.offset);
rlm@8 312 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
rlm@8 313 wbQ.enq(tagged WB_Load it.rdst);
rlm@8 314 end
rlm@8 315
rlm@8 316 tagged SW .it :
rlm@8 317 begin
punk@63 318 let val_rbase <- rf.rd1(it.rbase);
punk@63 319 let val_rsrc2 <- rf.rd2(it.rsrc);
punk@63 320 Addr addr = val_rbase + sext(it.offset);
punk@63 321 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:val_rsrc2 } );
rlm@8 322 wbQ.enq(tagged WB_Store);
rlm@8 323 end
rlm@8 324
rlm@8 325 // -- Simple Ops ------------------------------------------------
rlm@8 326
rlm@8 327 tagged ADDIU .it :
rlm@8 328 begin
punk@63 329 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 330 Bit#(32) result = val_rsrc1 + sext(it.imm);
rlm@8 331 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
rlm@8 332 end
punk@63 333 tagged SLTI .it :
punk@63 334 begin
punk@63 335 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 336 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( val_rsrc1, sext(it.imm) )});
punk@63 337 end
punk@63 338 tagged SLTIU .it :
punk@63 339 begin
punk@63 340 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 341 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( val_rsrc1, sext(it.imm) ) });
punk@63 342 end
rlm@8 343 tagged ANDI .it :
rlm@8 344 begin
punk@63 345 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 346 Bit#(32) zext_it_imm = zext(it.imm);
punk@63 347 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 & zext_it_imm)} );
rlm@8 348 end
rlm@8 349 tagged ORI .it :
rlm@8 350 begin
punk@63 351 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 352 Bit#(32) zext_it_imm = zext(it.imm);
punk@63 353 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(val_rsrc1 | zext_it_imm)} );
rlm@8 354 end
rlm@8 355 tagged XORI .it :
rlm@8 356 begin
punk@63 357 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 358 Bit#(32) zext_it_imm = zext(it.imm);
punk@63 359 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 ^ zext_it_imm )});
rlm@8 360 end
rlm@8 361 tagged LUI .it :
rlm@8 362 begin
rlm@8 363 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 364 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
rlm@8 365 end
rlm@8 366
rlm@8 367 tagged SLL .it :
rlm@8 368 begin
punk@63 369 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 370 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@63 371 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << zext_it_shamt )} );
rlm@8 372 end
rlm@8 373 tagged SRL .it :
rlm@8 374 begin
punk@63 375 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 376 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@63 377 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> zext_it_shamt )});
rlm@8 378 end
rlm@8 379 tagged SRA .it :
rlm@8 380 begin
punk@63 381 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 382 Bit#(32) zext_it_shamt = zext(it.shamt);
punk@63 383 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, zext_it_shamt )});
rlm@8 384 end
punk@63 385 tagged SLLV .it :
punk@63 386 begin
punk@63 387 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 388 let val_rshamt <- rf.rd2(it.rshamt);
punk@63 389 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 << rshft(val_rshamt) )});
punk@63 390 end
punk@63 391 tagged SRLV .it :
punk@63 392 begin
punk@63 393 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 394 let val_rshamt <- rf.rd2(it.rshamt);
punk@63 395 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc1 >> rshft(val_rshamt) )} );
punk@63 396 end
punk@63 397 tagged SRAV .it :
punk@63 398 begin
punk@63 399 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 400 let val_rshamt <- rf.rd2(it.rshamt);
punk@63 401 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( val_rsrc1, rshft(val_rshamt) ) });
punk@63 402 end
punk@63 403 tagged ADDU .it :
punk@63 404 begin
punk@63 405 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 406 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 407 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 + val_rsrc22 )} );
punk@63 408 end
punk@63 409 tagged SUBU .it :
punk@63 410 begin
punk@63 411 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 412 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 413 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 - val_rsrc22 )} );
punk@63 414 end
punk@63 415 tagged AND .it :
punk@63 416 begin
punk@63 417 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 418 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 419 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 & val_rsrc22 )} );
punk@63 420 end
punk@63 421 tagged OR .it :
punk@63 422 begin
punk@63 423 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 424 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 425 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 | val_rsrc22 )} );
punk@63 426 end
punk@63 427 tagged XOR .it :
punk@63 428 begin
punk@63 429 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 430 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 431 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(val_rsrc11 ^ val_rsrc22 )} );
punk@63 432 end
punk@63 433 tagged NOR .it :
punk@63 434 begin
punk@63 435 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 436 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 437 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(val_rsrc11 | val_rsrc22) )} );
punk@63 438 end
punk@63 439 tagged SLT .it :
punk@63 440 begin
punk@63 441 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 442 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 443 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( val_rsrc11, val_rsrc22 ) });
punk@63 444 end
punk@63 445 tagged SLTU .it :
punk@63 446 begin
punk@63 447 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 448 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 449 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( val_rsrc11, val_rsrc22 ) });
punk@63 450 end
rlm@8 451
rlm@8 452 // -- Branches --------------------------------------------------
rlm@8 453
rlm@8 454 tagged BLEZ .it :
punk@63 455 begin
punk@63 456 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 457 if ( signedLE( val_rsrc1, 0 ) )
punk@63 458 begin
rlm@8 459 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 460 branchTaken = True;
punk@63 461 end
punk@63 462 end
rlm@8 463
rlm@8 464 tagged BGTZ .it :
punk@63 465 begin
punk@63 466 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 467 if ( signedGT( val_rsrc1, 0 ) )
rlm@8 468 begin
rlm@8 469 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 470 branchTaken = True;
rlm@8 471 end
punk@63 472 end
rlm@8 473
rlm@8 474 tagged BLTZ .it :
punk@63 475 begin
punk@63 476 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 477 if ( signedLT( val_rsrc1, 0 ) )
rlm@8 478 begin
rlm@8 479 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 480 branchTaken = True;
rlm@8 481 end
punk@63 482 end
rlm@8 483
punk@63 484 tagged BGEZ .it :
punk@63 485 begin
punk@63 486 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 487 if ( signedGE( val_rsrc1, 0 ) )
punk@63 488 begin
punk@63 489 newPC = pc_plus4 + (sext(it.offset) << 2);
punk@63 490 branchTaken = True;
punk@63 491 end
punk@63 492 end
rlm@8 493
rlm@8 494 tagged BEQ .it :
punk@63 495 begin
punk@63 496 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 497 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 498 if ( val_rsrc11 == val_rsrc22 )
rlm@8 499 begin
rlm@8 500 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 501 branchTaken = True;
rlm@8 502 end
punk@63 503 end
rlm@8 504
rlm@8 505 tagged BNE .it :
punk@63 506 begin
punk@63 507 let val_rsrc11 <- rf.rd1(it.rsrc1);
punk@63 508 let val_rsrc22 <- rf.rd2(it.rsrc2);
punk@63 509 if ( val_rsrc11 != val_rsrc22 )
rlm@8 510 begin
rlm@8 511 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 512 branchTaken = True;
rlm@8 513 end
punk@63 514 end
rlm@8 515
rlm@8 516 // -- Jumps -----------------------------------------------------
rlm@8 517
rlm@8 518 tagged J .it :
punk@63 519 begin
rlm@8 520 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8 521 branchTaken = True;
rlm@8 522 end
rlm@8 523
rlm@8 524 tagged JR .it :
punk@42 525 begin
punk@63 526 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@63 527 newPC = val_rsrc1;
rlm@8 528 branchTaken = True;
rlm@8 529 end
rlm@8 530
rlm@8 531 tagged JAL .it :
rlm@8 532 begin
rlm@8 533 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
rlm@8 534 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8 535 branchTaken = True;
rlm@8 536 end
rlm@8 537
rlm@8 538 tagged JALR .it :
rlm@8 539 begin
punk@63 540 let val_rsrc1 <- rf.rd1(it.rsrc);
rlm@8 541 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
punk@63 542 newPC = val_rsrc1;
rlm@8 543 branchTaken = True;
rlm@8 544 end
rlm@8 545
rlm@8 546 // -- Cop0 ------------------------------------------------------
rlm@8 547
punk@33 548 tagged MTC0 .it : //Recieve things from host computer
rlm@8 549 begin
punk@63 550 let val_rsrc1 <- rf.rd1(it.rsrc);
punk@43 551 // $display( " PROCESSOR MTC0 call\n");
rlm@8 552 case ( it.cop0dst )
punk@63 553 5'd10 : cp0_statsEn <= unpack(truncate(val_rsrc1));
punk@63 554 5'd21 : cp0_tohost <= truncate(val_rsrc1);
punk@63 555 5'd26 : cp0_progComp <= unpack(truncate(val_rsrc1)); //states audio program completed and termination okay
punk@63 556 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(val_rsrc1))); //Bit size is 16 not 32
rlm@8 557 default :
rlm@8 558 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
rlm@8 559 endcase
rlm@8 560 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
rlm@8 561 end
rlm@8 562
rlm@8 563 //this is host stuff?
punk@33 564 tagged MFC0 .it : //Things out
rlm@8 565 begin
rlm@8 566 case ( it.cop0src )
rlm@8 567 // not actually an ALU instruction but don't have the format otherwise
rlm@8 568 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
rlm@8 569 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
rlm@8 570 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
punk@33 571 5'd25 : begin
punk@65 572 // $display( "**** EOF Requested");
punk@50 573 let sample = inAudioFifo.first();
punk@50 574 case (sample) matches
punk@50 575 tagged EndOfFile :
punk@50 576 begin
punk@50 577 $display("PROCESSOR sent toC EOF");
punk@50 578 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(True)) }); // Reading clears bit
punk@50 579 inAudioFifo.deq;
punk@50 580 end
punk@50 581 tagged Sample .data:
punk@50 582 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(False)) }); // Reading clears bit
punk@50 583 endcase
punk@33 584 end
punk@33 585 5'd28 : begin
punk@65 586 $display( "***** Reqesting Sample");
punk@33 587 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
punk@33 588 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
punk@43 589 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
punk@33 590 else $display ( "Audio File EOF Reached. Invalid sample request.");
punk@33 591 inAudioFifo.deq();
punk@33 592 end
rlm@8 593 default :
rlm@8 594 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
rlm@8 595 endcase
rlm@8 596 end
rlm@8 597
rlm@8 598 // -- Illegal ---------------------------------------------------
rlm@8 599
rlm@8 600 default :
rlm@8 601 $display( " RTL-ERROR : %m : Illegal instruction !" );
rlm@8 602
rlm@8 603 endcase
rlm@8 604
rlm@8 605 //evaluate branch prediction
rlm@8 606 Addr ppc = pcQ.first().qnxtpc; //predicted branch
rlm@8 607 if (ppc != newPC) //prediction wrong
rlm@8 608 begin
rlm@8 609 epoch <= pcQ.first().qepoch + 1;
rlm@8 610 bp.upd(instrpc, newPC); //update branch predictor
rlm@8 611 pcQ.clear();
rlm@8 612 pc <= newPC;
rlm@8 613 end
rlm@8 614 else
rlm@8 615 pcQ.deq();
rlm@49 616 //rlm: removing
rlm@49 617 // if ( cp0_statsEn )
rlm@49 618 // num_inst.incr();
rlm@8 619
rlm@8 620 endrule
rlm@8 621
rlm@8 622 rule writeback; // ( stage == Writeback );
rlm@8 623 traceTiny("mkProc", "writeback","W");
rlm@8 624
rlm@8 625
rlm@8 626 // get what to do off the writeback queue
rlm@8 627 wbQ.deq();
rlm@8 628 case (wbQ.first()) matches
rlm@8 629 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
rlm@8 630 tagged WB_Load .regWr :
rlm@8 631 begin
rlm@8 632 dataRespQ.deq();
rlm@8 633 if (dataRespQ.first() matches tagged LoadResp .ld)
rlm@8 634 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
rlm@8 635 end
rlm@8 636 tagged WB_Store : dataRespQ.deq();
rlm@8 637 tagged WB_Host .dat : noAction;
rlm@8 638 endcase
rlm@8 639
rlm@8 640 endrule
rlm@8 641
rlm@49 642 //rlm remove
rlm@49 643 // rule inc_num_cycles;
rlm@49 644 // if ( cp0_statsEn )
rlm@49 645 // num_cycles.incr();
rlm@49 646 // endrule
punk@11 647
punk@43 648 /*
punk@11 649 // for now, we don't do anything.
punk@43 650 rule connectAudioReqResp;
punk@43 651 $display("rlm: PROCESSOR copies a datum\n");
punk@43 652 outAudioFifo.enq(inAudioFifo.first());
punk@43 653 inAudioFifo.deq;
punk@43 654 endrule
punk@43 655 */
punk@50 656 /*
punk@33 657 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
punk@37 658 $display (" PROCESSOR End Audio Flag Set ");
punk@33 659 cp0_audioEOF <= True;
punk@33 660 inAudioFifo.deq;
punk@33 661 endrule
punk@50 662 */
punk@50 663 rule sendProcEnd (cp0_progComp);
punk@33 664 $display (" PROCESSOR Says Program Complete ");
punk@33 665 outAudioFifo.enq(tagged EndOfFile);
punk@33 666 cp0_progComp <= False; //only send one. And functions to reset
punk@11 667 endrule
punk@43 668
punk@12 669
rlm@8 670 //-----------------------------------------------------------
rlm@8 671 // Methods
rlm@8 672
rlm@8 673 interface Client imem_client;
punk@21 674 interface Get request = fifoToGet(instReqQ);
punk@21 675 interface Put response = fifoToPut(instRespQ);
rlm@8 676 endinterface
rlm@8 677
rlm@8 678 interface Client dmem_client;
punk@21 679 interface Get request = fifoToGet(dataReqQ);
punk@21 680 interface Put response = fifoToPut(dataRespQ);
rlm@8 681 endinterface
rlm@8 682
rlm@8 683 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
rlm@8 684
punk@36 685 /*
punk@36 686 interface CPUToHost tohost;
punk@36 687 method Bit#(32) cpuToHost(int req);
punk@36 688 return (case (req)
punk@36 689 0: cp0_tohost;
punk@36 690 1: pc;
punk@36 691 2: zeroExtend(pack(stage));
punk@36 692 endcase);
punk@36 693 endmethod
punk@36 694 endinterface
punk@36 695 */
punk@36 696
punk@21 697 interface Get sampleOutput = fifoToGet(outAudioFifo);
punk@36 698 interface Put sampleInput = fifoToPut(inAudioFifo);
punk@11 699
rlm@8 700 endmodule
rlm@8 701