annotate modules/bluespec/Pygar/lab4/FPGATypes.bsv @ 22:0cfbb1e2de22 pygar svn.23

[svn r23] whoohoo! it Compiles (note with commented out stuff)
author punk
date Wed, 28 Apr 2010 00:40:15 -0400
parents 74716e9a81cc
children
rev   line source
rlm@8 1 typedef 30 AvalonAddressWidth;
rlm@8 2 typedef 32 AvalonDataWidth;
rlm@8 3
rlm@8 4 // need length + 1 spacing between CBusGet/Puts
rlm@8 5 // Be warned - consider the word size of each address before
rlm@8 6 // assigning new ones!!!
rlm@8 7 // These are word addresses
rlm@8 8 // Multiply by 4 to get byte address
rlm@8 9 typedef 0 ToHostRegAddr;
rlm@8 10 typedef 4 FromHostRegAddr;
rlm@8 11 typedef 8 BreakpointRegAddr;
rlm@8 12 typedef 12 BreakpointClearedAddr;
rlm@8 13 typedef 16 PCRegAddr;
rlm@8 14 typedef 20 StatsEnRegAddr;
rlm@8 15 typedef 24 DCacheNumAccessesRegAddr;
rlm@8 16 typedef 28 DCacheNumMissesRegAddr;
rlm@8 17 typedef 32 DCacheNumWriteBacksRegAddr;
rlm@8 18 typedef 36 ICacheNumAccessesRegAddr;
rlm@8 19 typedef 40 ICacheNumMissesRegAddr;
rlm@8 20 typedef 44 ICacheNumWriteBacksRegAddr;
rlm@8 21 typedef 48 NumCyclesRegAddr;
rlm@8 22 typedef 52 NumInstRegAddr;
rlm@8 23 typedef 256 RegFileAddr; // The regfile is super long. Be careful of assigning conflicting addresses.
rlm@8 24