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annotate modules/bluespec/Pygar/core/Processor.bsv @ 38:05598d745f99 pygar svn.39

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[svn r39] fixed audiocorepipe
author punk
date Tue, 04 May 2010 19:27:38 -0400
parents 0475235d1513
children ced2ebd41347
rev   line source
rlm@8 1 /// The MIT License
rlm@8 2
rlm@8 3 // Copyright (c) 2009 Massachusetts Institute of Technology
rlm@8 4
rlm@8 5 // Permission is hereby granted, free of charge, to any person obtaining a copy
rlm@8 6 // of this software and associated documentation files (the "Software"), to deal
rlm@8 7 // in the Software without restriction, including without limitation the rights
rlm@8 8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rlm@8 9 // copies of the Software, and to permit persons to whom the Software is
rlm@8 10 // furnished to do so, subject to the following conditions:
rlm@8 11
rlm@8 12 // The above copyright notice and this permission notice shall be included in
rlm@8 13 // all copies or substantial portions of the Software.
rlm@8 14
rlm@8 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rlm@8 16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rlm@8 17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rlm@8 18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rlm@8 19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rlm@8 20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rlm@8 21 // THE SOFTWARE.
rlm@8 22
rlm@19 23
rlm@8 24 import Connectable::*;
rlm@8 25 import GetPut::*;
rlm@8 26 import ClientServer::*;
rlm@8 27 import RegFile::*;
rlm@8 28
rlm@8 29 import FIFO::*;
rlm@8 30 import FIFOF::*;
rlm@8 31 import SFIFO::*;
rlm@8 32 import RWire::*;
rlm@8 33
punk@11 34 import Trace::*;
rlm@8 35 import BFIFO::*;
rlm@8 36 import MemTypes::*;
rlm@8 37 import ProcTypes::*;
rlm@8 38 import BRegFile::*;
rlm@8 39 import BranchPred::*;
rlm@8 40 //import PathTypes::*; This is only there to force the debugging
rlm@8 41
rlm@8 42 //AWB includes
rlm@8 43 `include "asim/provides/low_level_platform_interface.bsh"
rlm@8 44 `include "asim/provides/soft_connections.bsh"
rlm@8 45 `include "asim/provides/common_services.bsh"
rlm@8 46
rlm@8 47 // Local includes
punk@11 48 //`include "asim/provides/processor_library.bsh" (included above directly)
punk@36 49
rlm@8 50 `include "asim/provides/common_services.bsh"
rlm@8 51 `include "asim/dict/STATS_PROCESSOR.bsh"
punk@26 52 `include "asim/provides/processor_library.bsh"
rlm@8 53
punk@11 54 // Local includes. Look for the correspondingly named .awb files
punk@11 55 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
punk@11 56 // to find the actual Bluespec files which are used to generate
punk@11 57 // these includes. These files are specific to this audio processing
punk@11 58 // pipeline
punk@11 59
punk@12 60 `include "asim/provides/audio_pipe_types.bsh"
rlm@8 61
punk@12 62 //interface CPUToHost;
punk@12 63 // method Bit#(32) cpuToHost(int req);
punk@12 64 //endinterface
rlm@8 65
rlm@8 66 interface Proc;
rlm@8 67
rlm@8 68 // Interface from processor to caches
rlm@8 69 interface Client#(DataReq,DataResp) dmem_client;
rlm@8 70 interface Client#(InstReq,InstResp) imem_client;
rlm@8 71
rlm@8 72 // Interface for enabling/disabling statistics on the rest of the core
rlm@8 73 interface Get#(Bool) statsEn_get;
rlm@8 74
punk@12 75 // // Interface to host
punk@12 76 // interface CPUToHost tohost;
rlm@8 77
punk@11 78 // Interface to Audio Pipeline
punk@15 79 interface Get#(AudioProcessorUnit) sampleOutput;
punk@36 80 interface Put#(AudioProcessorUnit) sampleInput;
punk@11 81
rlm@8 82 endinterface
rlm@8 83
rlm@8 84 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
rlm@8 85
rlm@8 86 //-----------------------------------------------------------
rlm@8 87 // Register file module
rlm@8 88 //-----------------------------------------------------------
rlm@8 89
rlm@8 90 interface BRFile;
rlm@8 91 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8 92 method Bit#(32) rd1( Rindx rindx );
rlm@8 93 method Bit#(32) rd2( Rindx rindx );
rlm@8 94 endinterface
rlm@8 95
rlm@8 96 module mkBRFile( BRFile );
rlm@8 97
rlm@8 98 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
rlm@8 99
rlm@8 100 method Action wr( Rindx rindx, Bit#(32) data );
rlm@8 101 rfile.upd( rindx, data );
rlm@8 102 endmethod
rlm@8 103
rlm@8 104 method Bit#(32) rd1( Rindx rindx );
rlm@8 105 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8 106 endmethod
rlm@8 107
rlm@8 108 method Bit#(32) rd2( Rindx rindx );
rlm@8 109 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
rlm@8 110 endmethod
rlm@8 111
rlm@8 112 endmodule
rlm@8 113
rlm@8 114 //-----------------------------------------------------------
rlm@8 115 // Helper functions
rlm@8 116 //-----------------------------------------------------------
rlm@8 117
rlm@8 118 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
rlm@8 119 return zeroExtend( pack( signedLT(val1,val2) ) );
rlm@8 120 endfunction
rlm@8 121
rlm@8 122 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
rlm@8 123 return zeroExtend( pack( val1 < val2 ) );
rlm@8 124 endfunction
rlm@8 125
rlm@8 126 function Bit#(32) rshft( Bit#(32) val );
rlm@8 127 return zeroExtend(val[4:0]);
rlm@8 128 endfunction
rlm@8 129
rlm@8 130
rlm@8 131 //-----------------------------------------------------------
rlm@8 132 // Find funct for wbQ
rlm@8 133 //-----------------------------------------------------------
rlm@8 134 function Bool findwbf(Rindx fVal, WBResult cmpVal);
rlm@8 135 case (cmpVal) matches
rlm@8 136 tagged WB_ALU {data:.res, dest:.rd} :
rlm@8 137 return (fVal == rd);
rlm@8 138 tagged WB_Load .rd :
rlm@8 139 return (fVal == rd);
rlm@8 140 tagged WB_Store .st :
rlm@8 141 return False;
rlm@8 142 tagged WB_Host .x :
rlm@8 143 return False;
rlm@8 144 endcase
rlm@8 145 endfunction
rlm@8 146
rlm@8 147
rlm@8 148 //-----------------------------------------------------------
rlm@8 149 // Stall funct for wbQ
rlm@8 150 //-----------------------------------------------------------
rlm@8 151 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
rlm@8 152 case (inst) matches
rlm@8 153 // -- Memory Ops ------------------------------------------------
rlm@8 154 tagged LW .it :
rlm@8 155 return f.find(it.rbase);
rlm@8 156 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
rlm@8 157 return (f.find(addr) || f.find2(dreg));
rlm@8 158
rlm@8 159 // -- Simple Ops ------------------------------------------------
rlm@8 160 tagged ADDIU .it : return f.find(it.rsrc);
rlm@8 161 tagged SLTI .it : return f.find(it.rsrc);
rlm@8 162 tagged SLTIU .it : return f.find(it.rsrc);
rlm@8 163 tagged ANDI .it : return f.find(it.rsrc);
rlm@8 164 tagged ORI .it : return f.find(it.rsrc);
rlm@8 165 tagged XORI .it : return f.find(it.rsrc);
rlm@8 166
rlm@8 167 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
rlm@8 168 tagged SLL .it : return f.find(it.rsrc);
rlm@8 169 tagged SRL .it : return f.find(it.rsrc);
rlm@8 170 tagged SRA .it : return f.find(it.rsrc);
rlm@8 171 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 172 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 173 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
rlm@8 174 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 175 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 176 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 177 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 178 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 179 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 180 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 181 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 182
rlm@8 183
rlm@8 184 // -- Branches --------------------------------------------------
rlm@8 185
rlm@8 186 tagged BLEZ .it : return (f.find(it.rsrc));
rlm@8 187 tagged BGTZ .it : return (f.find(it.rsrc));
rlm@8 188 tagged BLTZ .it : return (f.find(it.rsrc));
rlm@8 189 tagged BGEZ .it : return (f.find(it.rsrc));
rlm@8 190 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 191 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
rlm@8 192
rlm@8 193 // -- Jumps -----------------------------------------------------
rlm@8 194
rlm@8 195 tagged J .it : return False;
rlm@8 196 tagged JR .it : return f.find(it.rsrc);
rlm@8 197 tagged JALR .it : return f.find(it.rsrc);
rlm@8 198 tagged JAL .it : return False;
rlm@8 199
rlm@8 200 // -- Cop0 ------------------------------------------------------
rlm@8 201
rlm@8 202 tagged MTC0 .it : return f.find(it.rsrc);
rlm@8 203 tagged MFC0 .it : return False;
rlm@8 204
rlm@8 205 // -- Illegal ---------------------------------------------------
rlm@8 206
rlm@8 207 default : return False;
rlm@8 208
rlm@8 209 endcase
rlm@8 210 endfunction
rlm@8 211 //-----------------------------------------------------------
rlm@8 212 // Reference processor
rlm@8 213 //-----------------------------------------------------------
rlm@8 214
rlm@8 215
rlm@8 216 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
rlm@8 217 //(* synthesize *)
rlm@8 218
rlm@8 219 module [CONNECTED_MODULE] mkProc( Proc );
rlm@8 220
rlm@8 221 //-----------------------------------------------------------
rlm@8 222 // State
rlm@8 223
rlm@8 224 // Standard processor state
rlm@8 225
rlm@8 226 Reg#(Addr) pc <- mkReg(32'h00001000);
rlm@8 227 Reg#(Epoch) epoch <- mkReg(0);
rlm@8 228 Reg#(Stage) stage <- mkReg(PCgen);
rlm@8 229 BRFile rf <- mkBRFile;
rlm@8 230
rlm@8 231 // Branch Prediction
rlm@8 232 BranchPred bp <- mkBranchPred();
rlm@8 233 FIFO#(PCStat) execpc <- mkLFIFO();
rlm@8 234
rlm@8 235 // Pipelines
rlm@8 236 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
rlm@8 237 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
rlm@8 238
punk@33 239 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
rlm@8 240 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
rlm@8 241 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
rlm@8 242 Reg#(Bool) cp0_statsEn <- mkReg(False);
punk@33 243 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
punk@33 244 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
punk@33 245
rlm@8 246 // Memory request/response state
rlm@8 247
rlm@8 248 FIFO#(InstReq) instReqQ <- mkBFIFO1();
rlm@8 249 FIFO#(InstResp) instRespQ <- mkFIFO();
rlm@8 250
rlm@8 251 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
rlm@8 252 FIFO#(DataResp) dataRespQ <- mkFIFO();
rlm@8 253
punk@11 254 // Audio I/O
punk@11 255 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
punk@11 256 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
punk@11 257
punk@11 258
punk@11 259 // Statistics state (2010)
rlm@35 260 // Reg#(Stat) num_cycles <- mkReg(0);
rlm@35 261 // Reg#(Stat) num_inst <- mkReg(0);
rlm@8 262
rlm@8 263 //Or:
punk@11 264 // Statistics state
punk@11 265 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
punk@11 266 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
rlm@8 267
rlm@8 268 //-----------------------------------------------------------
rlm@8 269 // Rules
rlm@8 270
rlm@8 271 (* descending_urgency = "exec, pcgen" *)
rlm@8 272 rule pcgen; //( stage == PCgen );
rlm@8 273 let pc_plus4 = pc + 4;
rlm@8 274
rlm@8 275 traceTiny("mkProc", "pc",pc);
rlm@8 276 traceTiny("mkProc", "pcgen","P");
rlm@8 277 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
rlm@8 278
rlm@8 279 let next_pc = bp.get(pc);
rlm@8 280 if (next_pc matches tagged Valid .npc)
rlm@8 281 begin
rlm@8 282 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
rlm@8 283 pc <= npc;
rlm@8 284 end
rlm@8 285 else
rlm@8 286 begin
rlm@8 287 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
rlm@8 288 pc <= pc_plus4;
rlm@8 289 end
rlm@8 290
rlm@8 291 endrule
rlm@8 292
rlm@8 293 rule discard (instRespQ.first() matches tagged LoadResp .ld
rlm@8 294 &&& ld.tag != epoch);
rlm@8 295 traceTiny("mkProc", "stage", "D");
rlm@8 296 instRespQ.deq();
rlm@8 297 endrule
rlm@8 298
rlm@8 299 (* conflict_free = "exec, writeback" *)
rlm@8 300 rule exec (instRespQ.first() matches tagged LoadResp.ld
rlm@8 301 &&& (ld.tag == epoch)
rlm@8 302 &&& unpack(ld.data) matches .inst
rlm@8 303 &&& !stall(inst, wbQ));
rlm@8 304
rlm@8 305 // Some abbreviations
rlm@8 306 let sext = signExtend;
rlm@8 307 let zext = zeroExtend;
rlm@8 308 let sra = signedShiftRight;
rlm@8 309
rlm@8 310 // Get the instruction
rlm@8 311
rlm@8 312 instRespQ.deq();
rlm@8 313 Instr inst
rlm@8 314 = case ( instRespQ.first() ) matches
rlm@8 315 tagged LoadResp .ld : return unpack(ld.data);
rlm@8 316 tagged StoreResp .st : return ?;
rlm@8 317 endcase;
rlm@8 318
rlm@8 319 // Get the PC info
rlm@8 320 let instrpc = pcQ.first().qpc;
rlm@8 321 let pc_plus4 = instrpc + 4;
rlm@8 322
rlm@8 323 Bool branchTaken = False;
rlm@8 324 Addr newPC = pc_plus4;
rlm@8 325
rlm@8 326 // Tracing
rlm@8 327 traceTiny("mkProc", "exec","X");
rlm@8 328 traceTiny("mkProc", "exInstTiny",inst);
rlm@8 329 traceFull("mkProc", "exInstFull",inst);
rlm@8 330
rlm@8 331 case ( inst ) matches
rlm@8 332
rlm@8 333 // -- Memory Ops ------------------------------------------------
rlm@8 334
rlm@8 335 tagged LW .it :
rlm@8 336 begin
rlm@8 337 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8 338 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
rlm@8 339 wbQ.enq(tagged WB_Load it.rdst);
rlm@8 340 end
rlm@8 341
rlm@8 342 tagged SW .it :
rlm@8 343 begin
rlm@8 344 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
rlm@8 345 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
rlm@8 346 wbQ.enq(tagged WB_Store);
rlm@8 347 end
rlm@8 348
rlm@8 349 // -- Simple Ops ------------------------------------------------
rlm@8 350
rlm@8 351 tagged ADDIU .it :
rlm@8 352 begin
rlm@8 353 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
rlm@8 354 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
rlm@8 355 end
rlm@8 356 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
rlm@8 357 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
rlm@8 358 tagged ANDI .it :
rlm@8 359 begin
rlm@8 360 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 361 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
rlm@8 362 end
rlm@8 363 tagged ORI .it :
rlm@8 364 begin
rlm@8 365 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 366 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
rlm@8 367 end
rlm@8 368 tagged XORI .it :
rlm@8 369 begin
rlm@8 370 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 371 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
rlm@8 372 end
rlm@8 373 tagged LUI .it :
rlm@8 374 begin
rlm@8 375 Bit#(32) zext_it_imm = zext(it.imm);
rlm@8 376 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
rlm@8 377 end
rlm@8 378
rlm@8 379 tagged SLL .it :
rlm@8 380 begin
rlm@8 381 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8 382 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
rlm@8 383 end
rlm@8 384 tagged SRL .it :
rlm@8 385 begin
rlm@8 386 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8 387 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
rlm@8 388 end
rlm@8 389 tagged SRA .it :
rlm@8 390 begin
rlm@8 391 Bit#(32) zext_it_shamt = zext(it.shamt);
rlm@8 392 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
rlm@8 393 end
rlm@8 394 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
rlm@8 395 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
rlm@8 396 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
rlm@8 397 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
rlm@8 398 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
rlm@8 399 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
rlm@8 400 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
rlm@8 401 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
rlm@8 402 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
rlm@8 403 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8 404 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
rlm@8 405
rlm@8 406 // -- Branches --------------------------------------------------
rlm@8 407
rlm@8 408 tagged BLEZ .it :
rlm@8 409 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
rlm@8 410 begin
rlm@8 411 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 412 branchTaken = True;
rlm@8 413 end
rlm@8 414
rlm@8 415 tagged BGTZ .it :
rlm@8 416 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
rlm@8 417 begin
rlm@8 418 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 419 branchTaken = True;
rlm@8 420 end
rlm@8 421
rlm@8 422 tagged BLTZ .it :
rlm@8 423 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
rlm@8 424 begin
rlm@8 425 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 426 branchTaken = True;
rlm@8 427 end
rlm@8 428
rlm@8 429 tagged BGEZ .it :
rlm@8 430 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
rlm@8 431 begin
rlm@8 432 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 433 branchTaken = True;
rlm@8 434 end
rlm@8 435
rlm@8 436 tagged BEQ .it :
rlm@8 437 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
rlm@8 438 begin
rlm@8 439 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 440 branchTaken = True;
rlm@8 441 end
rlm@8 442
rlm@8 443 tagged BNE .it :
rlm@8 444 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
rlm@8 445 begin
rlm@8 446 newPC = pc_plus4 + (sext(it.offset) << 2);
rlm@8 447 branchTaken = True;
rlm@8 448 end
rlm@8 449
rlm@8 450 // -- Jumps -----------------------------------------------------
rlm@8 451
rlm@8 452 tagged J .it :
rlm@8 453 begin
rlm@8 454 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8 455 branchTaken = True;
rlm@8 456 end
rlm@8 457
rlm@8 458 tagged JR .it :
rlm@8 459 begin
rlm@8 460 newPC = rf.rd1(it.rsrc);
rlm@8 461 branchTaken = True;
rlm@8 462 end
rlm@8 463
rlm@8 464 tagged JAL .it :
rlm@8 465 begin
rlm@8 466 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
rlm@8 467 newPC = { pc_plus4[31:28], it.target, 2'b0 };
rlm@8 468 branchTaken = True;
rlm@8 469 end
rlm@8 470
rlm@8 471 tagged JALR .it :
rlm@8 472 begin
rlm@8 473 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
rlm@8 474 newPC = rf.rd1(it.rsrc);
rlm@8 475 branchTaken = True;
rlm@8 476 end
rlm@8 477
rlm@8 478 // -- Cop0 ------------------------------------------------------
rlm@8 479
punk@33 480 tagged MTC0 .it : //Recieve things from host computer
rlm@8 481 begin
punk@33 482 $display( " PROCESSOR MTC0 call\n");
rlm@8 483 case ( it.cop0dst )
rlm@8 484 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
rlm@8 485 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
punk@33 486 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
punk@33 487 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32
rlm@8 488 default :
rlm@8 489 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
rlm@8 490 endcase
rlm@8 491 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
rlm@8 492 end
rlm@8 493
rlm@8 494 //this is host stuff?
punk@33 495 tagged MFC0 .it : //Things out
rlm@8 496 begin
punk@33 497 $display( " PROCESSOR MFC0 call\n");
rlm@8 498 case ( it.cop0src )
rlm@8 499 // not actually an ALU instruction but don't have the format otherwise
rlm@8 500 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
rlm@8 501 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
rlm@8 502 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
punk@33 503 5'd25 : begin
punk@33 504 $display( "**** EOF Requested\n ");
punk@33 505 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit
punk@33 506 cp0_audioEOF <= False;
punk@33 507 end
punk@33 508 5'd28 : begin
punk@33 509 $display( "***** Reqesting Sample \n");
punk@33 510 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
punk@33 511 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
punk@33 512 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
punk@33 513 else $display ( "Audio File EOF Reached. Invalid sample request.");
punk@33 514 inAudioFifo.deq();
punk@33 515 end
rlm@8 516 default :
rlm@8 517 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
rlm@8 518 endcase
rlm@8 519 end
rlm@8 520
rlm@8 521 // -- Illegal ---------------------------------------------------
rlm@8 522
rlm@8 523 default :
rlm@8 524 $display( " RTL-ERROR : %m : Illegal instruction !" );
rlm@8 525
rlm@8 526 endcase
rlm@8 527
rlm@8 528 //evaluate branch prediction
rlm@8 529 Addr ppc = pcQ.first().qnxtpc; //predicted branch
rlm@8 530 if (ppc != newPC) //prediction wrong
rlm@8 531 begin
rlm@8 532 epoch <= pcQ.first().qepoch + 1;
rlm@8 533 bp.upd(instrpc, newPC); //update branch predictor
rlm@8 534 pcQ.clear();
rlm@8 535 pc <= newPC;
rlm@8 536 end
rlm@8 537 else
rlm@8 538 pcQ.deq();
rlm@8 539
rlm@8 540 if ( cp0_statsEn )
punk@11 541 num_inst.incr();
rlm@8 542
rlm@8 543 endrule
rlm@8 544
rlm@8 545 rule writeback; // ( stage == Writeback );
rlm@8 546 traceTiny("mkProc", "writeback","W");
rlm@8 547
rlm@8 548
rlm@8 549 // get what to do off the writeback queue
rlm@8 550 wbQ.deq();
rlm@8 551 case (wbQ.first()) matches
rlm@8 552 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
rlm@8 553 tagged WB_Load .regWr :
rlm@8 554 begin
rlm@8 555 dataRespQ.deq();
rlm@8 556 if (dataRespQ.first() matches tagged LoadResp .ld)
rlm@8 557 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
rlm@8 558 end
rlm@8 559 tagged WB_Store : dataRespQ.deq();
rlm@8 560 tagged WB_Host .dat : noAction;
rlm@8 561 endcase
rlm@8 562
rlm@8 563 endrule
rlm@8 564
rlm@8 565 rule inc_num_cycles;
rlm@8 566 if ( cp0_statsEn )
punk@11 567 num_cycles.incr();
rlm@8 568 endrule
punk@11 569
punk@11 570
punk@11 571 // for now, we don't do anything.
punk@33 572 // rule connectAudioReqResp;
punk@25 573 // $display("rlm: PROCESSOR copies a datum\n");
punk@33 574 // outAudioFifo.enq(inAudioFifo.first());
punk@33 575 // inAudioFifo.deq;
punk@33 576 // endrule
punk@33 577
punk@33 578 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
punk@37 579 $display (" PROCESSOR End Audio Flag Set ");
punk@33 580 cp0_audioEOF <= True;
punk@33 581 inAudioFifo.deq;
punk@33 582 endrule
punk@33 583
punk@33 584 rule sendAudioEnd (cp0_progComp);
punk@33 585 $display (" PROCESSOR Says Program Complete ");
punk@33 586 outAudioFifo.enq(tagged EndOfFile);
punk@33 587 cp0_progComp <= False; //only send one. And functions to reset
punk@11 588 endrule
rlm@8 589
punk@12 590
rlm@8 591 //-----------------------------------------------------------
rlm@8 592 // Methods
rlm@8 593
rlm@8 594 interface Client imem_client;
punk@21 595 interface Get request = fifoToGet(instReqQ);
punk@21 596 interface Put response = fifoToPut(instRespQ);
rlm@8 597 endinterface
rlm@8 598
rlm@8 599 interface Client dmem_client;
punk@21 600 interface Get request = fifoToGet(dataReqQ);
punk@21 601 interface Put response = fifoToPut(dataRespQ);
rlm@8 602 endinterface
rlm@8 603
rlm@8 604 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
rlm@8 605
punk@36 606 /*
punk@36 607 interface CPUToHost tohost;
punk@36 608 method Bit#(32) cpuToHost(int req);
punk@36 609 return (case (req)
punk@36 610 0: cp0_tohost;
punk@36 611 1: pc;
punk@36 612 2: zeroExtend(pack(stage));
punk@36 613 endcase);
punk@36 614 endmethod
punk@36 615 endinterface
punk@36 616 */
punk@36 617
punk@21 618 interface Get sampleOutput = fifoToGet(outAudioFifo);
punk@36 619 interface Put sampleInput = fifoToPut(inAudioFifo);
punk@11 620
rlm@8 621 endmodule
rlm@8 622