view modules/bluespec/Pygar/core/Processor.bsv @ 38:05598d745f99 pygar svn.39

[svn r39] fixed audiocorepipe
author punk
date Tue, 04 May 2010 19:27:38 -0400
parents 0475235d1513
children ced2ebd41347
line wrap: on
line source
1 /// The MIT License
3 // Copyright (c) 2009 Massachusetts Institute of Technology
5 // Permission is hereby granted, free of charge, to any person obtaining a copy
6 // of this software and associated documentation files (the "Software"), to deal
7 // in the Software without restriction, including without limitation the rights
8 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 // copies of the Software, and to permit persons to whom the Software is
10 // furnished to do so, subject to the following conditions:
12 // The above copyright notice and this permission notice shall be included in
13 // all copies or substantial portions of the Software.
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 // THE SOFTWARE.
24 import Connectable::*;
25 import GetPut::*;
26 import ClientServer::*;
27 import RegFile::*;
29 import FIFO::*;
30 import FIFOF::*;
31 import SFIFO::*;
32 import RWire::*;
34 import Trace::*;
35 import BFIFO::*;
36 import MemTypes::*;
37 import ProcTypes::*;
38 import BRegFile::*;
39 import BranchPred::*;
40 //import PathTypes::*; This is only there to force the debugging
42 //AWB includes
43 `include "asim/provides/low_level_platform_interface.bsh"
44 `include "asim/provides/soft_connections.bsh"
45 `include "asim/provides/common_services.bsh"
47 // Local includes
48 //`include "asim/provides/processor_library.bsh" (included above directly)
50 `include "asim/provides/common_services.bsh"
51 `include "asim/dict/STATS_PROCESSOR.bsh"
52 `include "asim/provides/processor_library.bsh"
54 // Local includes. Look for the correspondingly named .awb files
55 // workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
56 // to find the actual Bluespec files which are used to generate
57 // these includes. These files are specific to this audio processing
58 // pipeline
60 `include "asim/provides/audio_pipe_types.bsh"
62 //interface CPUToHost;
63 // method Bit#(32) cpuToHost(int req);
64 //endinterface
66 interface Proc;
68 // Interface from processor to caches
69 interface Client#(DataReq,DataResp) dmem_client;
70 interface Client#(InstReq,InstResp) imem_client;
72 // Interface for enabling/disabling statistics on the rest of the core
73 interface Get#(Bool) statsEn_get;
75 // // Interface to host
76 // interface CPUToHost tohost;
78 // Interface to Audio Pipeline
79 interface Get#(AudioProcessorUnit) sampleOutput;
80 interface Put#(AudioProcessorUnit) sampleInput;
82 endinterface
84 typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
86 //-----------------------------------------------------------
87 // Register file module
88 //-----------------------------------------------------------
90 interface BRFile;
91 method Action wr( Rindx rindx, Bit#(32) data );
92 method Bit#(32) rd1( Rindx rindx );
93 method Bit#(32) rd2( Rindx rindx );
94 endinterface
96 module mkBRFile( BRFile );
98 RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
100 method Action wr( Rindx rindx, Bit#(32) data );
101 rfile.upd( rindx, data );
102 endmethod
104 method Bit#(32) rd1( Rindx rindx );
105 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
106 endmethod
108 method Bit#(32) rd2( Rindx rindx );
109 return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
110 endmethod
112 endmodule
114 //-----------------------------------------------------------
115 // Helper functions
116 //-----------------------------------------------------------
118 function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
119 return zeroExtend( pack( signedLT(val1,val2) ) );
120 endfunction
122 function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
123 return zeroExtend( pack( val1 < val2 ) );
124 endfunction
126 function Bit#(32) rshft( Bit#(32) val );
127 return zeroExtend(val[4:0]);
128 endfunction
131 //-----------------------------------------------------------
132 // Find funct for wbQ
133 //-----------------------------------------------------------
134 function Bool findwbf(Rindx fVal, WBResult cmpVal);
135 case (cmpVal) matches
136 tagged WB_ALU {data:.res, dest:.rd} :
137 return (fVal == rd);
138 tagged WB_Load .rd :
139 return (fVal == rd);
140 tagged WB_Store .st :
141 return False;
142 tagged WB_Host .x :
143 return False;
144 endcase
145 endfunction
148 //-----------------------------------------------------------
149 // Stall funct for wbQ
150 //-----------------------------------------------------------
151 function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
152 case (inst) matches
153 // -- Memory Ops ------------------------------------------------
154 tagged LW .it :
155 return f.find(it.rbase);
156 tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
157 return (f.find(addr) || f.find2(dreg));
159 // -- Simple Ops ------------------------------------------------
160 tagged ADDIU .it : return f.find(it.rsrc);
161 tagged SLTI .it : return f.find(it.rsrc);
162 tagged SLTIU .it : return f.find(it.rsrc);
163 tagged ANDI .it : return f.find(it.rsrc);
164 tagged ORI .it : return f.find(it.rsrc);
165 tagged XORI .it : return f.find(it.rsrc);
167 tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself
168 tagged SLL .it : return f.find(it.rsrc);
169 tagged SRL .it : return f.find(it.rsrc);
170 tagged SRA .it : return f.find(it.rsrc);
171 tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
172 tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
173 tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt));
174 tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
175 tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
176 tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
177 tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
178 tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
179 tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
180 tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
181 tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
184 // -- Branches --------------------------------------------------
186 tagged BLEZ .it : return (f.find(it.rsrc));
187 tagged BGTZ .it : return (f.find(it.rsrc));
188 tagged BLTZ .it : return (f.find(it.rsrc));
189 tagged BGEZ .it : return (f.find(it.rsrc));
190 tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
191 tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
193 // -- Jumps -----------------------------------------------------
195 tagged J .it : return False;
196 tagged JR .it : return f.find(it.rsrc);
197 tagged JALR .it : return f.find(it.rsrc);
198 tagged JAL .it : return False;
200 // -- Cop0 ------------------------------------------------------
202 tagged MTC0 .it : return f.find(it.rsrc);
203 tagged MFC0 .it : return False;
205 // -- Illegal ---------------------------------------------------
207 default : return False;
209 endcase
210 endfunction
211 //-----------------------------------------------------------
212 // Reference processor
213 //-----------------------------------------------------------
216 //(* doc = "synthesis attribute ram_style mkProc distributed;" *)
217 //(* synthesize *)
219 module [CONNECTED_MODULE] mkProc( Proc );
221 //-----------------------------------------------------------
222 // State
224 // Standard processor state
226 Reg#(Addr) pc <- mkReg(32'h00001000);
227 Reg#(Epoch) epoch <- mkReg(0);
228 Reg#(Stage) stage <- mkReg(PCgen);
229 BRFile rf <- mkBRFile;
231 // Branch Prediction
232 BranchPred bp <- mkBranchPred();
233 FIFO#(PCStat) execpc <- mkLFIFO();
235 // Pipelines
236 FIFO#(PCStat) pcQ <-mkSizedFIFO(3);
237 SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
239 // NEED TO ADD CAPABILITY FOR RESET (should be able to just say if I get valid in and these are flagged, clear them.
240 Reg#(Bit#(32)) cp0_tohost <- mkReg(0);
241 Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
242 Reg#(Bool) cp0_statsEn <- mkReg(False);
243 Reg#(Bool) cp0_audioEOF <- mkReg(False); // Register to let code that EOF is reached
244 Reg#(Bool) cp0_progComp <- mkReg(False); // Register to let processor know that the program is complete (as this terminates)
246 // Memory request/response state
248 FIFO#(InstReq) instReqQ <- mkBFIFO1();
249 FIFO#(InstResp) instRespQ <- mkFIFO();
251 FIFO#(DataReq) dataReqQ <- mkBFIFO1();
252 FIFO#(DataResp) dataRespQ <- mkFIFO();
254 // Audio I/O
255 FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
256 FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
259 // Statistics state (2010)
260 // Reg#(Stat) num_cycles <- mkReg(0);
261 // Reg#(Stat) num_inst <- mkReg(0);
263 //Or:
264 // Statistics state
265 STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
266 STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
268 //-----------------------------------------------------------
269 // Rules
271 (* descending_urgency = "exec, pcgen" *)
272 rule pcgen; //( stage == PCgen );
273 let pc_plus4 = pc + 4;
275 traceTiny("mkProc", "pc",pc);
276 traceTiny("mkProc", "pcgen","P");
277 instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
279 let next_pc = bp.get(pc);
280 if (next_pc matches tagged Valid .npc)
281 begin
282 pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
283 pc <= npc;
284 end
285 else
286 begin
287 pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
288 pc <= pc_plus4;
289 end
291 endrule
293 rule discard (instRespQ.first() matches tagged LoadResp .ld
294 &&& ld.tag != epoch);
295 traceTiny("mkProc", "stage", "D");
296 instRespQ.deq();
297 endrule
299 (* conflict_free = "exec, writeback" *)
300 rule exec (instRespQ.first() matches tagged LoadResp.ld
301 &&& (ld.tag == epoch)
302 &&& unpack(ld.data) matches .inst
303 &&& !stall(inst, wbQ));
305 // Some abbreviations
306 let sext = signExtend;
307 let zext = zeroExtend;
308 let sra = signedShiftRight;
310 // Get the instruction
312 instRespQ.deq();
313 Instr inst
314 = case ( instRespQ.first() ) matches
315 tagged LoadResp .ld : return unpack(ld.data);
316 tagged StoreResp .st : return ?;
317 endcase;
319 // Get the PC info
320 let instrpc = pcQ.first().qpc;
321 let pc_plus4 = instrpc + 4;
323 Bool branchTaken = False;
324 Addr newPC = pc_plus4;
326 // Tracing
327 traceTiny("mkProc", "exec","X");
328 traceTiny("mkProc", "exInstTiny",inst);
329 traceFull("mkProc", "exInstFull",inst);
331 case ( inst ) matches
333 // -- Memory Ops ------------------------------------------------
335 tagged LW .it :
336 begin
337 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
338 dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
339 wbQ.enq(tagged WB_Load it.rdst);
340 end
342 tagged SW .it :
343 begin
344 Addr addr = rf.rd1(it.rbase) + sext(it.offset);
345 dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
346 wbQ.enq(tagged WB_Store);
347 end
349 // -- Simple Ops ------------------------------------------------
351 tagged ADDIU .it :
352 begin
353 Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
354 wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
355 end
356 tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
357 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
358 tagged ANDI .it :
359 begin
360 Bit#(32) zext_it_imm = zext(it.imm);
361 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
362 end
363 tagged ORI .it :
364 begin
365 Bit#(32) zext_it_imm = zext(it.imm);
366 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
367 end
368 tagged XORI .it :
369 begin
370 Bit#(32) zext_it_imm = zext(it.imm);
371 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
372 end
373 tagged LUI .it :
374 begin
375 Bit#(32) zext_it_imm = zext(it.imm);
376 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
377 end
379 tagged SLL .it :
380 begin
381 Bit#(32) zext_it_shamt = zext(it.shamt);
382 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
383 end
384 tagged SRL .it :
385 begin
386 Bit#(32) zext_it_shamt = zext(it.shamt);
387 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
388 end
389 tagged SRA .it :
390 begin
391 Bit#(32) zext_it_shamt = zext(it.shamt);
392 wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
393 end
394 tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
395 tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
396 tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
397 tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
398 tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
399 tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
400 tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
401 tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
402 tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
403 tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
404 tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
406 // -- Branches --------------------------------------------------
408 tagged BLEZ .it :
409 if ( signedLE( rf.rd1(it.rsrc), 0 ) )
410 begin
411 newPC = pc_plus4 + (sext(it.offset) << 2);
412 branchTaken = True;
413 end
415 tagged BGTZ .it :
416 if ( signedGT( rf.rd1(it.rsrc), 0 ) )
417 begin
418 newPC = pc_plus4 + (sext(it.offset) << 2);
419 branchTaken = True;
420 end
422 tagged BLTZ .it :
423 if ( signedLT( rf.rd1(it.rsrc), 0 ) )
424 begin
425 newPC = pc_plus4 + (sext(it.offset) << 2);
426 branchTaken = True;
427 end
429 tagged BGEZ .it :
430 if ( signedGE( rf.rd1(it.rsrc), 0 ) )
431 begin
432 newPC = pc_plus4 + (sext(it.offset) << 2);
433 branchTaken = True;
434 end
436 tagged BEQ .it :
437 if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
438 begin
439 newPC = pc_plus4 + (sext(it.offset) << 2);
440 branchTaken = True;
441 end
443 tagged BNE .it :
444 if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
445 begin
446 newPC = pc_plus4 + (sext(it.offset) << 2);
447 branchTaken = True;
448 end
450 // -- Jumps -----------------------------------------------------
452 tagged J .it :
453 begin
454 newPC = { pc_plus4[31:28], it.target, 2'b0 };
455 branchTaken = True;
456 end
458 tagged JR .it :
459 begin
460 newPC = rf.rd1(it.rsrc);
461 branchTaken = True;
462 end
464 tagged JAL .it :
465 begin
466 wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
467 newPC = { pc_plus4[31:28], it.target, 2'b0 };
468 branchTaken = True;
469 end
471 tagged JALR .it :
472 begin
473 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
474 newPC = rf.rd1(it.rsrc);
475 branchTaken = True;
476 end
478 // -- Cop0 ------------------------------------------------------
480 tagged MTC0 .it : //Recieve things from host computer
481 begin
482 $display( " PROCESSOR MTC0 call\n");
483 case ( it.cop0dst )
484 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
485 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc));
486 5'd26 : cp0_progComp <= unpack(truncate(rf.rd1(it.rsrc))); //states audio program completed and termination okay
487 5'd27 : outAudioFifo.enq(tagged Sample unpack(truncate(rf.rd1(it.rsrc)))); //Bit size is 16 not 32
488 default :
489 $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
490 endcase
491 wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
492 end
494 //this is host stuff?
495 tagged MFC0 .it : //Things out
496 begin
497 $display( " PROCESSOR MFC0 call\n");
498 case ( it.cop0src )
499 // not actually an ALU instruction but don't have the format otherwise
500 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
501 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
502 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost });
503 5'd25 : begin
504 $display( "**** EOF Requested\n ");
505 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_audioEOF)) }); // Reading clears bit
506 cp0_audioEOF <= False;
507 end
508 5'd28 : begin
509 $display( "***** Reqesting Sample \n");
510 let sample = inAudioFifo.first(); // is this going to cause perf. delay?
511 if (sample matches tagged Sample .audio) // if it is EOF another rule sets the cp0_audioEOF
512 wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(audio)) }); // do I need pack?
513 else $display ( "Audio File EOF Reached. Invalid sample request.");
514 inAudioFifo.deq();
515 end
516 default :
517 $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
518 endcase
519 end
521 // -- Illegal ---------------------------------------------------
523 default :
524 $display( " RTL-ERROR : %m : Illegal instruction !" );
526 endcase
528 //evaluate branch prediction
529 Addr ppc = pcQ.first().qnxtpc; //predicted branch
530 if (ppc != newPC) //prediction wrong
531 begin
532 epoch <= pcQ.first().qepoch + 1;
533 bp.upd(instrpc, newPC); //update branch predictor
534 pcQ.clear();
535 pc <= newPC;
536 end
537 else
538 pcQ.deq();
540 if ( cp0_statsEn )
541 num_inst.incr();
543 endrule
545 rule writeback; // ( stage == Writeback );
546 traceTiny("mkProc", "writeback","W");
549 // get what to do off the writeback queue
550 wbQ.deq();
551 case (wbQ.first()) matches
552 tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
553 tagged WB_Load .regWr :
554 begin
555 dataRespQ.deq();
556 if (dataRespQ.first() matches tagged LoadResp .ld)
557 rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate?
558 end
559 tagged WB_Store : dataRespQ.deq();
560 tagged WB_Host .dat : noAction;
561 endcase
563 endrule
565 rule inc_num_cycles;
566 if ( cp0_statsEn )
567 num_cycles.incr();
568 endrule
571 // for now, we don't do anything.
572 // rule connectAudioReqResp;
573 // $display("rlm: PROCESSOR copies a datum\n");
574 // outAudioFifo.enq(inAudioFifo.first());
575 // inAudioFifo.deq;
576 // endrule
578 rule flagAudioEnd (inAudioFifo.first() matches tagged EndOfFile);
579 $display (" PROCESSOR End Audio Flag Set ");
580 cp0_audioEOF <= True;
581 inAudioFifo.deq;
582 endrule
584 rule sendAudioEnd (cp0_progComp);
585 $display (" PROCESSOR Says Program Complete ");
586 outAudioFifo.enq(tagged EndOfFile);
587 cp0_progComp <= False; //only send one. And functions to reset
588 endrule
591 //-----------------------------------------------------------
592 // Methods
594 interface Client imem_client;
595 interface Get request = fifoToGet(instReqQ);
596 interface Put response = fifoToPut(instRespQ);
597 endinterface
599 interface Client dmem_client;
600 interface Get request = fifoToGet(dataReqQ);
601 interface Put response = fifoToPut(dataRespQ);
602 endinterface
604 interface Get statsEn_get = toGet(asReg(cp0_statsEn));
606 /*
607 interface CPUToHost tohost;
608 method Bit#(32) cpuToHost(int req);
609 return (case (req)
610 0: cp0_tohost;
611 1: pc;
612 2: zeroExtend(pack(stage));
613 endcase);
614 endmethod
615 endinterface
616 */
618 interface Get sampleOutput = fifoToGet(outAudioFifo);
619 interface Put sampleInput = fifoToPut(inAudioFifo);
621 endmodule