Mercurial > pygar
changeset 20:a346d9e5118a pygar svn.21
[svn r21] deleted emacs save files
| author | rlm |
|---|---|
| date | Tue, 27 Apr 2010 23:43:41 -0400 |
| parents | 9910c032f38d |
| children | cffe0829ce14 |
| files | modules/bluespec/Pygar/core/#AudioCoreSystem.cpp# modules/bluespec/Pygar/core/#audioCorePipeline.bsv# modules/bluespec/Pygar/core/#olCore.bsv# modules/bluespec/Pygar/core/AudioCoreRRR.cpp~ modules/bluespec/Pygar/core/AudioCoreRRR.h~ modules/bluespec/Pygar/core/AudioCoreSystem.cpp~ modules/bluespec/Pygar/core/AudioCoreSystem.h~ modules/bluespec/Pygar/core/AudioPipeTypes.bsv~ modules/bluespec/Pygar/core/ProcTypes.bsv~ modules/bluespec/Pygar/core/Processor.bsv~ modules/bluespec/Pygar/core/audioCore.bsv~ modules/bluespec/Pygar/core/audioCorePipeline.bsv~ modules/bluespec/Pygar/core/audio_core.awb~ modules/bluespec/Pygar/core/audio_core_pipe.awb~ modules/bluespec/Pygar/core/audio_core_systems.awb~ modules/bluespec/Pygar/core/audio_pipe_types.awb~ modules/bluespec/Pygar/core/processor.awb~ |
| diffstat | 17 files changed, 0 insertions(+), 1966 deletions(-) [+] |
line wrap: on
line diff
1.1 --- a/modules/bluespec/Pygar/core/#AudioCoreSystem.cpp# Tue Apr 27 23:31:38 2010 -0400 1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 1.3 @@ -1,146 +0,0 @@ 1.4 -#include <stdio.h> 1.5 -#include <pthread.h> 1.6 -#include <semaphore.h> 1.7 - 1.8 -#include "asim/provides/connected_application.h" 1.9 -#include "asim/provides/stats_device.h" 1.10 -//#include "asim/provides/SndfileWavUtil.h" 1.11 - 1.12 -//#include "asim/rrr/client_stub_AUDIOCORERRR.h" 1.13 - 1.14 -using namespace std; 1.15 - 1.16 -pthread_mutex_t CONNECTED_APPLICATION_CLASS::lock; 1.17 -pthread_cond_t CONNECTED_APPLICATION_CLASS::cond; 1.18 -sem_t CONNECTED_APPLICATION_CLASS::throttle; 1.19 - 1.20 -// constructor 1.21 -CONNECTED_APPLICATION_CLASS::CONNECTED_APPLICATION_CLASS(VIRTUAL_PLATFORM vp) : 1.22 - clientStub(new AUDIOCORERRR_CLIENT_STUB_CLASS(this)) 1.23 -{ 1.24 -} 1.25 - 1.26 -// destructor 1.27 -CONNECTED_APPLICATION_CLASS::~CONNECTED_APPLICATION_CLASS() 1.28 -{ 1.29 -} 1.30 - 1.31 -// init 1.32 -void 1.33 -CONNECTED_APPLICATION_CLASS::Init() 1.34 -{ 1.35 - 1.36 - pthread_mutex_init(&lock, NULL); 1.37 - pthread_cond_init(&cond, NULL); 1.38 - sem_init(&throttle, 0, 64); 1.39 - 1.40 - // enable stats 1.41 - STATS_DEVICE_SERVER_CLASS::GetInstance()->SetupStats(); 1.42 -} 1.43 - 1.44 -void 1.45 -CONNECTED_APPLICATION_CLASS::UpdateSemaphore() 1.46 -{ 1.47 - sem_post(&throttle); 1.48 -} 1.49 - 1.50 -void 1.51 -CONNECTED_APPLICATION_CLASS::EndSimulation() 1.52 -{ 1.53 - printf("EndSimulation Called\n"); 1.54 - fflush(stdout); 1.55 - pthread_mutex_lock(&lock); 1.56 - // Do something about the race occuring here 1.57 - pthread_cond_signal(&cond); 1.58 - pthread_mutex_unlock(&lock); 1.59 - printf("EndSimulation done\n"); 1.60 - fflush(stdout); 1.61 -} 1.62 - 1.63 -// main 1.64 -void 1.65 -CONNECTED_APPLICATION_CLASS::Main() 1.66 -{ 1.67 - FILE *inputFile; 1.68 - UINT16 sample; 1.69 - 1.70 - // Convert input wav to pcm 1.71 - generate_pcm("input.wav","input.pcm"); 1.72 - 1.73 - //Send data to the machine here. 1.74 - inputFile = fopen("input.pcm","r"); 1.75 - assert(inputFile); 1.76 - 1.77 - 1.78 - int count = 0; 1.79 - 1.80 - printf("main: about to enter loop %d\n", count); 1.81 - 1.82 - while(fread(&sample, 2, 1, inputFile)) { 1.83 - if(count%1000 == 0) 1.84 - printf("main: %d\n", count); 1.85 - count++; 1.86 - sem_wait(&throttle); 1.87 - clientStub->SendUnprocessedStream(Data,(UINT32)sample); 1.88 - } 1.89 - 1.90 - printf("main: out of loop\n"); 1.91 - 1.92 - // Need to put lock here to prevent potential race condition 1.93 - pthread_mutex_lock(&lock); 1.94 - clientStub->SendUnprocessedStream(EndOfFile,0); 1.95 - 1.96 - printf("main: wait for end of file\n"); 1.97 - 1.98 - pthread_cond_wait(&cond, &lock); 1.99 - pthread_mutex_unlock(&lock); 1.100 - 1.101 - printf("main: lastt data out\n"); 1.102 - 1.103 - // Convert input wav to pcm 1.104 - generate_wav("out_hw.pcm","input.wav","out_hw.wav"); 1.105 - 1.106 - printf("generate wav done\n"); 1.107 - 1.108 - fflush(stdout); 1.109 - exit(0); 1.110 -} 1.111 - 1.112 -/* THIS IS THE CODE HANDLING FROM THE REGULAR SOFT-CORE 1.113 -TO BE INCORPORATED 1.114 -// main 1.115 -void 1.116 -CONNECTED_APPLICATION_CLASS::Main() 1.117 -{ 1.118 - int sleepCount = 0; 1.119 - int result = 0; 1.120 - 1.121 - fflush(stdout); 1.122 - 1.123 - while ((result = clientStub->ReadCPUToHost(0)) != 1) { 1.124 - sleep(1); 1.125 - //printf("System controller sleeps with result: %d\n", result); 1.126 - sleepCount++; 1.127 - if(sleepCount == 100) { 1.128 - printf("Failed to get response from hardware, bailing\n\n"); 1.129 - printf("This means that either your hardware is hanging\n"); 1.130 - printf("or that the software hasn't given it enough time\n"); 1.131 - printf("to complete. If you think it needs more time, then\n"); 1.132 - printf("edit CONNECTED_APPLICATION_CLASS::Main() in ProcessorSystem.cpp\n"); 1.133 - printf("(connected_application)\n"); 1.134 - exit(0); 1.135 - } 1.136 - } 1.137 - 1.138 - if(result == 1) { 1.139 - printf("\n***PASSED***\n"); 1.140 - } 1.141 - 1.142 - // Dump the stats file 1.143 - 1.144 - STATS_DEVICE_SERVER_CLASS::GetInstance()->DumpStats(); 1.145 - STATS_DEVICE_SERVER_CLASS::GetInstance()->EmitFile(); 1.146 - 1.147 - fflush(stdout); 1.148 - exit(0); 1.149 -}*/
2.1 --- a/modules/bluespec/Pygar/core/#audioCorePipeline.bsv# Tue Apr 27 23:31:38 2010 -0400 2.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 2.3 @@ -1,94 +0,0 @@ 2.4 -// The MIT License 2.5 - 2.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 2.7 - 2.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 2.9 -// of this software and associated documentation files (the "Software"), to deal 2.10 -// in the Software without restriction, including without limitation the rights 2.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 2.12 -// copies of the Software, and to permit persons to whom the Software is 2.13 -// furnished to do so, subject to the following conditions: 2.14 - 2.15 -// The above copyright notice and this permission notice shall be included in 2.16 -// all copies or substantial portions of the Software. 2.17 - 2.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 2.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2.24 -// THE SOFTWARE. 2.25 - 2.26 -// Author: Kermin Fleming kfleming@mit.edu 2.27 - 2.28 -import Connectable::*; 2.29 -import GetPut::*; 2.30 -import ClientServer::*; 2.31 -import FIFO::*; 2.32 - 2.33 -//AWB includes 2.34 -`include "asim/provides/low_level_platform_interface.bsh" 2.35 -`include "asim/provides/soft_connections.bsh" 2.36 -`include "asim/provides/common_services.bsh" 2.37 - 2.38 -//Local includes 2.39 -`include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface 2.40 -`include "asim/provides/core.bsh" 2.41 - 2.42 -`include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" 2.43 -`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" 2.44 - 2.45 -module [CONNECTED_MODULE] mkConnectedApplication (); 2.46 - Core core <- mkCore; 2.47 - Reg#(int) cycle <- mkReg(0); 2.48 - 2.49 - //External memory 2.50 - // I'm not comfortable assuming that the memory subsystem is in order 2.51 - // So I'll insert a completion buffer here. 2.52 - ClientStub_AUDICORERRR client_stub <- mkClientStub_AUDIOCORERRR(); 2.53 - // Make this big enough so that several outstanding requests may be supported 2.54 - FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); 2.55 - 2.56 - // this is for the tracing 2.57 - rule printCycles; 2.58 - cycle <= cycle+1; 2.59 - $fdisplay(stderr, " => Cycle = %d", cycle); 2.60 - endrule 2.61 - 2.62 - rule sendMemReq; 2.63 - let coreReq <- core.mmem_client.request.get; 2.64 - case (coreReq) matches 2.65 - tagged LoadReq .load: begin 2.66 - //Allocate ROB space 2.67 - client_stub.makeRequest_MemoryRequestLoad(load.addr); 2.68 - tags.enq(load.tag); 2.69 - end 2.70 - tagged StoreReq .store: begin 2.71 - client_stub.makeRequest_MemoryRequestStore(store.addr,store.data); 2.72 - end 2.73 - endcase 2.74 - endrule 2.75 - 2.76 - rule receiveMemResp; 2.77 - let memResp <- client_stub.getResponse_MemoryRequestLoad(); 2.78 - tags.deq; 2.79 - core.mmem_client.response.put(tagged LoadResp {data:memResp, 2.80 - tag: tags.first}); 2.81 - endrule 2.82 - 2.83 - // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together. 2.84 - 2.85 - rule feedOutput; 2.86 - let pipelineData <- core.sampleOutput.get(); 2.87 - AudioProcessorControl endOfFileTag = EndOfFile; 2.88 - AudioProcessorControl sampleTag = Data; 2.89 - 2.90 - case (pipelineData) matches 2.91 - tagged EndOfFile: client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?); 2.92 - tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), 2.93 - zeroExtend(pack(sample))); 2.94 - endcase 2.95 - endrule 2.96 - 2.97 -endmodule
3.1 --- a/modules/bluespec/Pygar/core/#olCore.bsv# Tue Apr 27 23:31:38 2010 -0400 3.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 3.3 @@ -1,90 +0,0 @@ 3.4 -// The MIT License 3.5 - 3.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 3.7 - 3.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 3.9 -// of this software and associated documentation files (the "Software"), to deal 3.10 -// in the Software without restriction, including without limitation the rights 3.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 3.12 -// copies of the Software, and to permit persons to whom the Software is 3.13 -// furnished to do so, subject to the following conditions: 3.14 - 3.15 -// The above copyright notice and this permission notice shall be included in 3.16 -// all copies or substantial portions of the Software. 3.17 - 3.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 3.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 3.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 3.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 3.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 3.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 3.24 -// THE SOFTWARE. 3.25 - 3.26 -import Connectable::*; 3.27 -import GetPut::*; 3.28 -import ClientServer::*; 3.29 - 3.30 - 3.31 -import DataCacheBlocking::*; 3.32 -import InstCacheBlocking::*; 3.33 -import Processor::*; 3.34 -import MemArb::*; 3.35 -import MemTypes::*; 3.36 - 3.37 -`include "asim/provides/data_cache.bsh" 3.38 -`include "asim/provides/instruction_cache.bsh" 3.39 - 3.40 -interface CoreStats; 3.41 - interface DCacheStats dcache; 3.42 - interface ICacheStats icache; 3.43 - interface ProcStats proc; 3.44 -endinterface 3.45 - 3.46 -interface Core; 3.47 - 3.48 - // Interface from core to main memory 3.49 - interface Client#(MainMemReq,MainMemResp) mmem_client; 3.50 - 3.51 - // Statistics 3.52 - interface CoreStats stats; 3.53 - 3.54 - // CPU to Host 3.55 - interface CPUToHost tohost; 3.56 - 3.57 - // Interface to Audio Pipeline 3.58 - interface Audio audio; 3.59 - 3.60 -endinterface 3.61 - 3.62 -(* synthesize *) 3.63 -module mkCore(Core); 3.64 - 3.65 - // Instantiate the modules 3.66 - Proc proc <- mkProc(); 3.67 - ICache#(InstReq,InstResp) icache <- mkInstCache(); 3.68 - DCache#(DataReq,DataResp) dcache <- mkDataCache(); 3.69 - MemArb marb <- mkMemArb(); 3.70 - 3.71 - // Internal connections 3.72 - mkConnection( proc.statsEn_get, icache.statsEn_put ); 3.73 - mkConnection( proc.statsEn_get, dcache.statsEn_put ); 3.74 - mkConnection( proc.imem_client, icache.proc_server ); 3.75 - mkConnection( proc.dmem_client, dcache.proc_server ); 3.76 - mkConnection( icache.mmem_client, marb.cache0_server ); 3.77 - mkConnection( dcache.mmem_client, marb.cache1_server ); 3.78 - 3.79 - // Methods 3.80 - interface mmem_client = marb.mmem_client; 3.81 - 3.82 - interface CoreStats stats; 3.83 - interface dcache = dcache.stats; 3.84 - interface icache = icache.stats; 3.85 - interface proc = proc.stats; 3.86 - endinterface 3.87 - 3.88 - interface CPUToHost tohost = proc.tohost; 3.89 - 3.90 - interface Audio audio = proc.audio; 3.91 - 3.92 -endmodule 3.93 -
4.1 --- a/modules/bluespec/Pygar/core/AudioCoreRRR.cpp~ Tue Apr 27 23:31:38 2010 -0400 4.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 4.3 @@ -1,118 +0,0 @@ 4.4 -#include <cstdio> 4.5 -#include <cstdlib> 4.6 -#include <iostream> 4.7 -#include <iomanip> 4.8 -#include <stdio.h> 4.9 -#include <sys/stat.h> 4.10 - 4.11 -#include "asim/rrr/service_ids.h" 4.12 - 4.13 -#include "asim/provides/connected_application.h" 4.14 - 4.15 - 4.16 - 4.17 -using namespace std; 4.18 - 4.19 -// ===== service instantiation ===== 4.20 -AUDIOCORERRR_SERVER_CLASS AUDIOCORERRR_SERVER_CLASS::instance; 4.21 - 4.22 -// constructor 4.23 -AUDIOCORERRR_SERVER_CLASS::AUDIOCORERRR_SERVER_CLASS() : 4.24 - serverStub(new AUDICORERRR_SERVER_STUB_CLASS(this)) 4.25 -{ 4.26 - // instantiate stub 4.27 - printf("AUDIOCORERRR init called\n"); 4.28 - outputFile = NULL; 4.29 - memory = NULL; 4.30 - fflush(stdout); 4.31 -} 4.32 - 4.33 -// destructor 4.34 -AUDIOCORERRR_SERVER_CLASS::~AUDIOCORERRR_SERVER_CLASS() 4.35 -{ 4.36 - Cleanup(); 4.37 -} 4.38 - 4.39 -// init 4.40 -void 4.41 -AUDIOCORERRR_SERVER_CLASS::Init(PLATFORMS_MODULE p) 4.42 -{ 4.43 - parent = p; 4.44 -} 4.45 - 4.46 -// uninit 4.47 -void 4.48 -AUDIOCORERRR_SERVER_CLASS::Uninit() 4.49 -{ 4.50 - Cleanup(); 4.51 -} 4.52 - 4.53 -// cleanup 4.54 -void 4.55 -AUDIOCORERRR_SERVER_CLASS::Cleanup() 4.56 -{ 4.57 - delete serverStub; 4.58 -} 4.59 - 4.60 - 4.61 -// 4.62 -// RRR service methods 4.63 -// 4.64 - 4.65 -UINT32 4.66 -AUDIOCORERRR_SERVER_CLASS::MemoryRequestLoad (UINT32 address) 4.67 -{ 4.68 - UINT32 returnVal; 4.69 - 4.70 - if(memory == NULL) { 4.71 - memory = new FUNCP_SIMULATED_MEMORY_CLASS(); 4.72 - } 4.73 - 4.74 - 4.75 - memory->Read(0,(UINT64) address, sizeof(UINT32), &returnVal); 4.76 - return returnVal; 4.77 -} 4.78 - 4.79 -void 4.80 -AUDIOCORERRR_SERVER_CLASS::MemoryRequestStore (UINT32 address, UINT32 data) 4.81 -{ 4.82 - if(memory == NULL) { 4.83 - memory = new FUNCP_SIMULATED_MEMORY_CLASS(); 4.84 - } 4.85 - 4.86 - memory->Write(0,(UINT64) address, sizeof(UINT32), &data); 4.87 - 4.88 -void 4.89 - 4.90 -AUDIOCORERRR_SERVER_CLASS::SendProcessedStream(UINT16 control, UINT16 data) 4.91 -{ 4.92 - 4.93 - AudioProcessorControl audioProcessorControl = (AudioProcessorControl) control; 4.94 - switch(control) { 4.95 - case EndOfFile: 4.96 - if(outputFile != NULL) { 4.97 - fflush(outputFile); 4.98 - fclose(outputFile); 4.99 - outputFile = NULL; 4.100 - } else { 4.101 - outputFile = fopen("out_hw.pcm","w"); 4.102 - assert(outputFile); 4.103 - fflush(outputFile); 4.104 - fclose(outputFile); 4.105 - } 4.106 - 4.107 - // Long term this should be in the data portion. But until I have code running, keep it here. 4.108 - CONNECTED_APPLICATION_CLASS::EndSimulation(); 4.109 - break; 4.110 - 4.111 - case Data: 4.112 - if(outputFile == NULL) { 4.113 - outputFile = fopen("out_hw.pcm","w"); 4.114 - assert(outputFile); 4.115 - } 4.116 - 4.117 - CONNECTED_APPLICATION_CLASS::UpdateSemaphore(); 4.118 - fwrite(&data, 2,1 , outputFile); 4.119 - break; 4.120 - } 4.121 -}
5.1 --- a/modules/bluespec/Pygar/core/AudioCoreRRR.h~ Tue Apr 27 23:31:38 2010 -0400 5.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 5.3 @@ -1,53 +0,0 @@ 5.4 - 5.5 -#ifndef _PROCESSORSYSTEMRRR_ 5.6 -#define _PROCESSORSYSTEMRRR_ 5.7 - 5.8 -#include <stdio.h> 5.9 -#include <sys/time.h> 5.10 - 5.11 -#include "asim/provides/low_level_platform_interface.h" 5.12 -#include "asim/provides/funcp_simulated_memory.h" 5.13 -#include "asim/provides/rrr.h" 5.14 - 5.15 - 5.16 - 5.17 -typedef class PROCESSORSYSTEMRRR_SERVER_CLASS* PROCESSORSYSTEMRRR_SERVER; 5.18 -class PROCESSORSYSTEMRRR_SERVER_CLASS: public RRR_SERVER_CLASS, public PLATFORMS_MODULE_CLASS 5.19 -{ 5.20 - private: 5.21 - // self-instantiation 5.22 - static PROCESSORSYSTEMRRR_SERVER_CLASS instance; 5.23 - FUNCP_SIMULATED_MEMORY_CLASS *memory; 5.24 - 5.25 - 5.26 - // server stub 5.27 - RRR_SERVER_STUB serverStub; 5.28 - 5.29 - int count; 5.30 - 5.31 - public: 5.32 - PROCESSORSYSTEMRRR_SERVER_CLASS(); 5.33 - ~PROCESSORSYSTEMRRR_SERVER_CLASS(); 5.34 - 5.35 - // static methods 5.36 - static PROCESSORSYSTEMRRR_SERVER GetInstance() { return &instance; } 5.37 - 5.38 - // required RRR methods 5.39 - void Init(PLATFORMS_MODULE); 5.40 - void Uninit(); 5.41 - void Cleanup(); 5.42 - 5.43 - // 5.44 - // RRR service methods 5.45 - // 5.46 - 5.47 - UINT32 MemoryRequestLoad (UINT32 address); 5.48 - void MemoryRequestStore (UINT32 address, UINT32 data); 5.49 -}; 5.50 - 5.51 - 5.52 - 5.53 -// include server stub 5.54 -#include "asim/rrr/server_stub_PROCESSORSYSTEMRRR.h" 5.55 - 5.56 -#endif
6.1 --- a/modules/bluespec/Pygar/core/AudioCoreSystem.cpp~ Tue Apr 27 23:31:38 2010 -0400 6.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 6.3 @@ -1,104 +0,0 @@ 6.4 -#include <stdio.h> 6.5 -#include <pthread.h> 6.6 -#include <semaphore.h> 6.7 - 6.8 -#include "asim/provides/connected_application.h" 6.9 -//#include "asim/provides/SndfileWavUtil.h" 6.10 - 6.11 -#include "asim/rrr/client_stub_AUDIOPROCESSORRRR.h" 6.12 - 6.13 -using namespace std; 6.14 - 6.15 -pthread_mutex_t CONNECTED_APPLICATION_CLASS::lock; 6.16 -pthread_cond_t CONNECTED_APPLICATION_CLASS::cond; 6.17 -sem_t CONNECTED_APPLICATION_CLASS::throttle; 6.18 - 6.19 -// constructor 6.20 -CONNECTED_APPLICATION_CLASS::CONNECTED_APPLICATION_CLASS(VIRTUAL_PLATFORM vp) : 6.21 - clientStub(new AUDIOPROCESSORRRR_CLIENT_STUB_CLASS(this)) 6.22 -{ 6.23 -} 6.24 - 6.25 -// destructor 6.26 -CONNECTED_APPLICATION_CLASS::~CONNECTED_APPLICATION_CLASS() 6.27 -{ 6.28 -} 6.29 - 6.30 -// init 6.31 -void 6.32 -CONNECTED_APPLICATION_CLASS::Init() 6.33 -{ 6.34 - 6.35 - pthread_mutex_init(&lock, NULL); 6.36 - pthread_cond_init(&cond, NULL); 6.37 - sem_init(&throttle, 0, 64); 6.38 - 6.39 -} 6.40 - 6.41 -void 6.42 -CONNECTED_APPLICATION_CLASS::UpdateSemaphore() 6.43 -{ 6.44 - sem_post(&throttle); 6.45 -} 6.46 - 6.47 -void 6.48 -CONNECTED_APPLICATION_CLASS::EndSimulation() 6.49 -{ 6.50 - printf("EndSimulation Called\n"); 6.51 - fflush(stdout); 6.52 - pthread_mutex_lock(&lock); 6.53 - // Do something about the race occuring here 6.54 - pthread_cond_signal(&cond); 6.55 - pthread_mutex_unlock(&lock); 6.56 - printf("EndSimulation done\n"); 6.57 - fflush(stdout); 6.58 -} 6.59 - 6.60 -// main 6.61 -void 6.62 -CONNECTED_APPLICATION_CLASS::Main() 6.63 -{ 6.64 - FILE *inputFile; 6.65 - UINT16 sample; 6.66 - 6.67 - // Convert input wav to pcm 6.68 - generate_pcm("input.wav","input.pcm"); 6.69 - 6.70 - //Send data to the machine here. 6.71 - inputFile = fopen("input.pcm","r"); 6.72 - assert(inputFile); 6.73 - 6.74 - 6.75 - int count = 0; 6.76 - 6.77 - printf("main: about to enter loop %d\n", count); 6.78 - 6.79 - while(fread(&sample, 2, 1, inputFile)) { 6.80 - if(count%1000 == 0) 6.81 - printf("main: %d\n", count); 6.82 - count++; 6.83 - sem_wait(&throttle); 6.84 - clientStub->SendUnprocessedStream(Data,(UINT32)sample); 6.85 - } 6.86 - 6.87 - printf("main: out of loop\n"); 6.88 - 6.89 - // Need to put lock here to prevent potential race condition 6.90 - pthread_mutex_lock(&lock); 6.91 - clientStub->SendUnprocessedStream(EndOfFile,0); 6.92 - 6.93 - printf("main: wait for end of file\n"); 6.94 - 6.95 - pthread_cond_wait(&cond, &lock); 6.96 - pthread_mutex_unlock(&lock); 6.97 - 6.98 - printf("main: lastt data out\n"); 6.99 - 6.100 - // Convert input wav to pcm 6.101 - generate_wav("out_hw.pcm","input.wav","out_hw.wav"); 6.102 - 6.103 - printf("generate wav done\n"); 6.104 - 6.105 - fflush(stdout); 6.106 - exit(0); 6.107 -}
7.1 --- a/modules/bluespec/Pygar/core/AudioCoreSystem.h~ Tue Apr 27 23:31:38 2010 -0400 7.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 7.3 @@ -1,56 +0,0 @@ 7.4 -// 7.5 -// INTEL CONFIDENTIAL 7.6 -// Copyright (c) 2008 Intel Corp. Recipient is granted a non-sublicensable 7.7 -// copyright license under Intel copyrights to copy and distribute this code 7.8 -// internally only. This code is provided "AS IS" with no support and with no 7.9 -// warranties of any kind, including warranties of MERCHANTABILITY, 7.10 -// FITNESS FOR ANY PARTICULAR PURPOSE or INTELLECTUAL PROPERTY INFRINGEMENT. 7.11 -// By making any use of this code, Recipient agrees that no other licenses 7.12 -// to any Intel patents, trade secrets, copyrights or other intellectual 7.13 -// property rights are granted herein, and no other licenses shall arise by 7.14 -// estoppel, implication or by operation of law. Recipient accepts all risks 7.15 -// of use. 7.16 -// 7.17 - 7.18 -// possibly use include paths to hide existing modules? 7.19 - 7.20 -#ifndef __AUDIO_CORE_CONNECTED_APPLICATION__ 7.21 -#define __AUDIO_CORE_CONNECTED_APPLICATION__ 7.22 - 7.23 -#include <stdio.h> 7.24 -#include <pthread.h> 7.25 -#include <semaphore.h> 7.26 - 7.27 -#include "asim/provides/virtual_platform.h" 7.28 - 7.29 -#include "asim/rrr/client_stub_AUDIOPROCESSORRRR.h" 7.30 - 7.31 -typedef enum { 7.32 - EndOfFile = 0, 7.33 - Data = 1 7.34 -} AudioProcessorControl; 7.35 - 7.36 - 7.37 -typedef class CONNECTED_APPLICATION_CLASS* CONNECTED_APPLICATION; 7.38 -class CONNECTED_APPLICATION_CLASS : public PLATFORMS_MODULE_CLASS 7.39 -{ 7.40 - private: 7.41 - AUDIOPROCESSORRRR_CLIENT_STUB clientStub; 7.42 - static sem_t throttle; 7.43 - static pthread_mutex_t lock; 7.44 - static pthread_cond_t cond; 7.45 - 7.46 - public: 7.47 - CONNECTED_APPLICATION_CLASS(VIRTUAL_PLATFORM vp); 7.48 - ~CONNECTED_APPLICATION_CLASS(); 7.49 - static void EndSimulation(); 7.50 - static void UpdateSemaphore(); 7.51 - 7.52 - // init 7.53 - void Init(); 7.54 - 7.55 - // main 7.56 - void Main(); 7.57 -}; 7.58 - 7.59 -#endif
8.1 --- a/modules/bluespec/Pygar/core/AudioPipeTypes.bsv~ Tue Apr 27 23:31:38 2010 -0400 8.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 8.3 @@ -1,53 +0,0 @@ 8.4 - 8.5 -// The MIT License 8.6 - 8.7 -// Copyright (c) 2009 Massachusetts Institute of Technology 8.8 - 8.9 -// Permission is hereby granted, free of charge, to any person obtaining a copy 8.10 -// of this software and associated documentation files (the "Software"), to deal 8.11 -// in the Software without restriction, including without limitation the rights 8.12 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8.13 -// copies of the Software, and to permit persons to whom the Software is 8.14 -// furnished to do so, subject to the following conditions: 8.15 - 8.16 -// The above copyright notice and this permission notice shall be included in 8.17 -// all copies or substantial portions of the Software. 8.18 - 8.19 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 8.20 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 8.21 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 8.22 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 8.23 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 8.24 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 8.25 -// THE SOFTWARE. 8.26 - 8.27 -// Author: Ker 8.28 -// min Fleming kfleming@mit.edu 8.29 - 8.30 -import Connectable::*; 8.31 -import GetPut::*; 8.32 -import ClientServer::*; 8.33 - 8.34 -typedef Int#(16) Sample; 8.35 - 8.36 -typedef enum { 8.37 - EndOfFile = 0, 8.38 - Data = 1 8.39 -} AudioProcessorControl deriving (Bits,Eq); 8.40 - 8.41 - 8.42 -typedef struct { 8.43 - Sample left; 8.44 - Sample right; 8.45 -} StereoSample deriving (Bits,Eq); 8.46 - 8.47 -typedef union tagged{ 8.48 - Sample Sample; 8.49 - void EndOfFile; 8.50 -} AudioProcessorUnit deriving (Bits,Eq); 8.51 - 8.52 -interface AudioPipeline; 8.53 - interface Put#(AudioProcessorUnit) sampleInput; 8.54 - interface Get#(AudioProcessorUnit) sampleOutput; 8.55 -endinterface 8.56 -
9.1 --- a/modules/bluespec/Pygar/core/ProcTypes.bsv~ Tue Apr 27 23:31:38 2010 -0400 9.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 9.3 @@ -1,375 +0,0 @@ 9.4 - 9.5 -import Trace::*; 9.6 - 9.7 -//---------------------------------------------------------------------- 9.8 -// Other typedefs 9.9 -//---------------------------------------------------------------------- 9.10 - 9.11 -typedef Bit#(32) Addr; 9.12 -typedef Int#(18) Stat; 9.13 - 9.14 -//---------------------------------------------------------------------- 9.15 -// Basic instruction type 9.16 -//---------------------------------------------------------------------- 9.17 - 9.18 -typedef Bit#(5) Rindx; 9.19 -typedef Bit#(16) Simm; 9.20 -typedef Bit#(16) Zimm; 9.21 -typedef Bit#(8) Epoch; 9.22 -typedef Bit#(5) Shamt; 9.23 -typedef Bit#(26) Target; 9.24 -typedef Bit#(5) CP0indx; 9.25 -typedef Bit#(32) Data; 9.26 - 9.27 -typedef enum 9.28 -{ 9.29 - Taken, 9.30 - NotTaken 9.31 -} 9.32 - Direction 9.33 - deriving(Bits,Eq); 9.34 - 9.35 - 9.36 -//---------------------------------------------------------------------- 9.37 -// Pipeline typedefs 9.38 -//---------------------------------------------------------------------- 9.39 - 9.40 -typedef union tagged 9.41 -{ 9.42 - Tuple2#(Rindx,Data) ALUWB; 9.43 - Rindx MemWB; 9.44 - Tuple2#(Rindx,Data) CoWB; 9.45 -} 9.46 - WritebackType 9.47 - deriving(Bits,Eq); 9.48 - 9.49 -//////////////////////// 9.50 -// I Add Writeback queue type 9.51 -//////////// 9.52 -typedef union tagged 9.53 -{ 9.54 - struct {Bit#(32) data; Rindx dest; } WB_ALU; 9.55 - Bit#(32) WB_Host; 9.56 - Rindx WB_Load; 9.57 - void WB_Store; 9.58 -} 9.59 -WBResult deriving(Eq, Bits); 9.60 - 9.61 -typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 9.62 -//typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits); 9.63 - 9.64 -typedef union tagged 9.65 -{ 9.66 - 9.67 - struct { Rindx rbase; Rindx rdst; Simm offset; } LW; 9.68 - struct { Rindx rbase; Rindx rsrc; Simm offset; } SW; 9.69 - 9.70 - struct { Rindx rsrc; Rindx rdst; Simm imm; } ADDIU; 9.71 - struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTI; 9.72 - struct { Rindx rsrc; Rindx rdst; Simm imm; } SLTIU; 9.73 - struct { Rindx rsrc; Rindx rdst; Zimm imm; } ANDI; 9.74 - struct { Rindx rsrc; Rindx rdst; Zimm imm; } ORI; 9.75 - struct { Rindx rsrc; Rindx rdst; Zimm imm; } XORI; 9.76 - struct { Rindx rdst; Zimm imm; } LUI; 9.77 - 9.78 - struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SLL; 9.79 - struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRL; 9.80 - struct { Rindx rsrc; Rindx rdst; Shamt shamt; } SRA; 9.81 - struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SLLV; 9.82 - struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRLV; 9.83 - struct { Rindx rsrc; Rindx rdst; Rindx rshamt; } SRAV; 9.84 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU; 9.85 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SUBU; 9.86 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } AND; 9.87 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } OR; 9.88 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } XOR; 9.89 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } NOR; 9.90 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLT; 9.91 - struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst; } SLTU; 9.92 - 9.93 - struct { Target target; } J; 9.94 - struct { Target target; } JAL; 9.95 - struct { Rindx rsrc; } JR; 9.96 - struct { Rindx rsrc; Rindx rdst; } JALR; 9.97 - struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BEQ; 9.98 - struct { Rindx rsrc1; Rindx rsrc2; Simm offset; } BNE; 9.99 - struct { Rindx rsrc; Simm offset; } BLEZ; 9.100 - struct { Rindx rsrc; Simm offset; } BGTZ; 9.101 - struct { Rindx rsrc; Simm offset; } BLTZ; 9.102 - struct { Rindx rsrc; Simm offset; } BGEZ; 9.103 - 9.104 - struct { Rindx rdst; CP0indx cop0src; } MFC0; 9.105 - struct { Rindx rsrc; CP0indx cop0dst; } MTC0; 9.106 - 9.107 - void ILLEGAL; 9.108 - 9.109 -} 9.110 -Instr deriving(Eq); 9.111 - 9.112 -//---------------------------------------------------------------------- 9.113 -// Pack and Unpack 9.114 -//---------------------------------------------------------------------- 9.115 - 9.116 -Bit#(6) opFUNC = 6'b000000; Bit#(6) fcSLL = 6'b000000; 9.117 -Bit#(6) opRT = 6'b000001; Bit#(6) fcSRL = 6'b000010; 9.118 -Bit#(6) opRS = 6'b010000; Bit#(6) fcSRA = 6'b000011; 9.119 - Bit#(6) fcSLLV = 6'b000100; 9.120 -Bit#(6) opLW = 6'b100011; Bit#(6) fcSRLV = 6'b000110; 9.121 -Bit#(6) opSW = 6'b101011; Bit#(6) fcSRAV = 6'b000111; 9.122 - Bit#(6) fcADDU = 6'b100001; 9.123 -Bit#(6) opADDIU = 6'b001001; Bit#(6) fcSUBU = 6'b100011; 9.124 -Bit#(6) opSLTI = 6'b001010; Bit#(6) fcAND = 6'b100100; 9.125 -Bit#(6) opSLTIU = 6'b001011; Bit#(6) fcOR = 6'b100101; 9.126 -Bit#(6) opANDI = 6'b001100; Bit#(6) fcXOR = 6'b100110; 9.127 -Bit#(6) opORI = 6'b001101; Bit#(6) fcNOR = 6'b100111; 9.128 -Bit#(6) opXORI = 6'b001110; Bit#(6) fcSLT = 6'b101010; 9.129 -Bit#(6) opLUI = 6'b001111; Bit#(6) fcSLTU = 6'b101011; 9.130 - 9.131 -Bit#(6) opJ = 6'b000010; 9.132 -Bit#(6) opJAL = 6'b000011; 9.133 -Bit#(6) fcJR = 6'b001000; 9.134 -Bit#(6) fcJALR = 6'b001001; 9.135 -Bit#(6) opBEQ = 6'b000100; 9.136 -Bit#(6) opBNE = 6'b000101; 9.137 -Bit#(6) opBLEZ = 6'b000110; 9.138 -Bit#(6) opBGTZ = 6'b000111; 9.139 -Bit#(5) rtBLTZ = 5'b00000; 9.140 -Bit#(5) rtBGEZ = 5'b00001; 9.141 - 9.142 -Bit#(5) rsMFC0 = 5'b00000; 9.143 -Bit#(5) rsMTC0 = 5'b00100; 9.144 - 9.145 -instance Bits#(Instr,32); 9.146 - 9.147 - // Pack Function 9.148 - 9.149 - function Bit#(32) pack( Instr instr ); 9.150 - 9.151 - case ( instr ) matches 9.152 - 9.153 - tagged LW .it : return { opLW, it.rbase, it.rdst, it.offset }; 9.154 - tagged SW .it : return { opSW, it.rbase, it.rsrc, it.offset }; 9.155 - 9.156 - tagged ADDIU .it : return { opADDIU, it.rsrc, it.rdst, it.imm }; 9.157 - tagged SLTI .it : return { opSLTI, it.rsrc, it.rdst, it.imm }; 9.158 - tagged SLTIU .it : return { opSLTIU, it.rsrc, it.rdst, it.imm }; 9.159 - tagged ANDI .it : return { opANDI, it.rsrc, it.rdst, it.imm }; 9.160 - tagged ORI .it : return { opORI, it.rsrc, it.rdst, it.imm }; 9.161 - tagged XORI .it : return { opXORI, it.rsrc, it.rdst, it.imm }; 9.162 - tagged LUI .it : return { opLUI, 5'b0, it.rdst, it.imm }; 9.163 - 9.164 - tagged SLL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL }; 9.165 - tagged SRL .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRL }; 9.166 - tagged SRA .it : return { opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSRA }; 9.167 - 9.168 - tagged SLLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSLLV }; 9.169 - tagged SRLV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRLV }; 9.170 - tagged SRAV .it : return { opFUNC, it.rshamt, it.rsrc, it.rdst, 5'b0, fcSRAV }; 9.171 - 9.172 - tagged ADDU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcADDU }; 9.173 - tagged SUBU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSUBU }; 9.174 - tagged AND .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcAND }; 9.175 - tagged OR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcOR }; 9.176 - tagged XOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcXOR }; 9.177 - tagged NOR .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcNOR }; 9.178 - tagged SLT .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLT }; 9.179 - tagged SLTU .it : return { opFUNC, it.rsrc1, it.rsrc2, it.rdst, 5'b0, fcSLTU }; 9.180 - 9.181 - tagged J .it : return { opJ, it.target }; 9.182 - tagged JAL .it : return { opJAL, it.target }; 9.183 - tagged JR .it : return { opFUNC, it.rsrc, 5'b0, 5'b0, 5'b0, fcJR }; 9.184 - tagged JALR .it : return { opFUNC, it.rsrc, 5'b0, it.rdst, 5'b0, fcJALR }; 9.185 - tagged BEQ .it : return { opBEQ, it.rsrc1, it.rsrc2, it.offset }; 9.186 - tagged BNE .it : return { opBNE, it.rsrc1, it.rsrc2, it.offset }; 9.187 - tagged BLEZ .it : return { opBLEZ, it.rsrc, 5'b0, it.offset }; 9.188 - tagged BGTZ .it : return { opBGTZ, it.rsrc, 5'b0, it.offset }; 9.189 - tagged BLTZ .it : return { opRT, it.rsrc, rtBLTZ, it.offset }; 9.190 - tagged BGEZ .it : return { opRT, it.rsrc, rtBGEZ, it.offset }; 9.191 - 9.192 - tagged MFC0 .it : return { opRS, rsMFC0, it.rdst, it.cop0src, 11'b0 }; 9.193 - tagged MTC0 .it : return { opRS, rsMTC0, it.rsrc, it.cop0dst, 11'b0 }; 9.194 - 9.195 - endcase 9.196 - 9.197 - endfunction 9.198 - 9.199 - // Unpack Function 9.200 - 9.201 - function Instr unpack( Bit#(32) instrBits ); 9.202 - 9.203 - let opcode = instrBits[ 31 : 26 ]; 9.204 - let rs = instrBits[ 25 : 21 ]; 9.205 - let rt = instrBits[ 20 : 16 ]; 9.206 - let rd = instrBits[ 15 : 11 ]; 9.207 - let shamt = instrBits[ 10 : 6 ]; 9.208 - let funct = instrBits[ 5 : 0 ]; 9.209 - let imm = instrBits[ 15 : 0 ]; 9.210 - let target = instrBits[ 25 : 0 ]; 9.211 - 9.212 - case ( opcode ) 9.213 - 9.214 - opLW : return LW { rbase:rs, rdst:rt, offset:imm }; 9.215 - opSW : return SW { rbase:rs, rsrc:rt, offset:imm }; 9.216 - opADDIU : return ADDIU { rsrc:rs, rdst:rt, imm:imm }; 9.217 - opSLTI : return SLTI { rsrc:rs, rdst:rt, imm:imm }; 9.218 - opSLTIU : return SLTIU { rsrc:rs, rdst:rt, imm:imm }; 9.219 - opANDI : return ANDI { rsrc:rs, rdst:rt, imm:imm }; 9.220 - opORI : return ORI { rsrc:rs, rdst:rt, imm:imm }; 9.221 - opXORI : return XORI { rsrc:rs, rdst:rt, imm:imm }; 9.222 - opLUI : return LUI { rdst:rt, imm:imm }; 9.223 - opJ : return J { target:target }; 9.224 - opJAL : return JAL { target:target }; 9.225 - opBEQ : return BEQ { rsrc1:rs, rsrc2:rt, offset:imm }; 9.226 - opBNE : return BNE { rsrc1:rs, rsrc2:rt, offset:imm }; 9.227 - opBLEZ : return BLEZ { rsrc:rs, offset:imm }; 9.228 - opBGTZ : return BGTZ { rsrc:rs, offset:imm }; 9.229 - 9.230 - opFUNC : 9.231 - case ( funct ) 9.232 - fcSLL : return SLL { rsrc:rt, rdst:rd, shamt:shamt }; 9.233 - fcSRL : return SRL { rsrc:rt, rdst:rd, shamt:shamt }; 9.234 - fcSRA : return SRA { rsrc:rt, rdst:rd, shamt:shamt }; 9.235 - fcSLLV : return SLLV { rsrc:rt, rdst:rd, rshamt:rs }; 9.236 - fcSRLV : return SRLV { rsrc:rt, rdst:rd, rshamt:rs }; 9.237 - fcSRAV : return SRAV { rsrc:rt, rdst:rd, rshamt:rs }; 9.238 - fcADDU : return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.239 - fcSUBU : return SUBU { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.240 - fcAND : return AND { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.241 - fcOR : return OR { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.242 - fcXOR : return XOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.243 - fcNOR : return NOR { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.244 - fcSLT : return SLT { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.245 - fcSLTU : return SLTU { rsrc1:rs, rsrc2:rt, rdst:rd }; 9.246 - fcJR : return JR { rsrc:rs }; 9.247 - fcJALR : return JALR { rsrc:rs, rdst:rd }; 9.248 - default : return ILLEGAL; 9.249 - endcase 9.250 - 9.251 - opRT : 9.252 - case ( rt ) 9.253 - rtBLTZ : return BLTZ { rsrc:rs, offset:imm }; 9.254 - rtBGEZ : return BGEZ { rsrc:rs, offset:imm }; 9.255 - default : return ILLEGAL; 9.256 - endcase 9.257 - 9.258 - opRS : 9.259 - case ( rs ) 9.260 - rsMFC0 : return MFC0 { rdst:rt, cop0src:rd }; 9.261 - rsMTC0 : return MTC0 { rsrc:rt, cop0dst:rd }; 9.262 - default : return ILLEGAL; 9.263 - endcase 9.264 - 9.265 - default : return ILLEGAL; 9.266 - 9.267 - endcase 9.268 - 9.269 - endfunction 9.270 - 9.271 -endinstance 9.272 - 9.273 -//---------------------------------------------------------------------- 9.274 -// Trace 9.275 -//---------------------------------------------------------------------- 9.276 - 9.277 -instance Traceable#(Instr); 9.278 - 9.279 - function Action traceTiny( String loc, String ttag, Instr inst ); 9.280 - case ( inst ) matches 9.281 - 9.282 - tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); 9.283 - tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); 9.284 - 9.285 - tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); 9.286 - tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); 9.287 - tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); 9.288 - tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); 9.289 - tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); 9.290 - tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); 9.291 - tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); 9.292 - 9.293 - tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); 9.294 - tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); 9.295 - tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); 9.296 - tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); 9.297 - tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); 9.298 - tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); 9.299 - 9.300 - tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); 9.301 - tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); 9.302 - tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); 9.303 - tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); 9.304 - tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); 9.305 - tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); 9.306 - tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); 9.307 - tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); 9.308 - 9.309 - tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); 9.310 - tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); 9.311 - tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); 9.312 - tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); 9.313 - tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); 9.314 - tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); 9.315 - tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); 9.316 - tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); 9.317 - tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); 9.318 - tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); 9.319 - 9.320 - tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); 9.321 - tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); 9.322 - 9.323 - tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); 9.324 - 9.325 - endcase 9.326 - endfunction 9.327 - 9.328 - function Action traceFull( String loc, String ttag, Instr inst ); 9.329 - case ( inst ) matches 9.330 - 9.331 - tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); 9.332 - tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); 9.333 - 9.334 - tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.335 - tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.336 - tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.337 - tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.338 - tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.339 - tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); 9.340 - tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); 9.341 - 9.342 - tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 9.343 - tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 9.344 - tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); 9.345 - tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 9.346 - tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 9.347 - tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); 9.348 - 9.349 - tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.350 - tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.351 - tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.352 - tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.353 - tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.354 - tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.355 - tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.356 - tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); 9.357 - 9.358 - tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); 9.359 - tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); 9.360 - tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); 9.361 - tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); 9.362 - tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 9.363 - tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); 9.364 - tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 9.365 - tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 9.366 - tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 9.367 - tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); 9.368 - 9.369 - tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); 9.370 - tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); 9.371 - 9.372 - tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); 9.373 - 9.374 - endcase 9.375 - endfunction 9.376 - 9.377 -endinstance 9.378 -
10.1 --- a/modules/bluespec/Pygar/core/Processor.bsv~ Tue Apr 27 23:31:38 2010 -0400 10.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 10.3 @@ -1,628 +0,0 @@ 10.4 -/// The MIT License 10.5 - 10.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 10.7 - 10.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 10.9 -// of this software and associated documentation files (the "Software"), to deal 10.10 -// in the Software without restriction, including without limitation the rights 10.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10.12 -// copies of the Software, and to permit persons to whom the Software is 10.13 -// furnished to do so, subject to the following conditions: 10.14 - 10.15 -// The above copyright notice and this permission notice shall be included in 10.16 -// all copies or substantial portions of the Software. 10.17 - 10.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 10.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 10.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 10.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 10.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 10.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 10.24 -// THE SOFTWARE. 10.25 - 10.26 -import Connectable::*; 10.27 -import GetPut::*; 10.28 -import ClientServer::*; 10.29 -import RegFile::*; 10.30 - 10.31 -import FIFO::*; 10.32 -import FIFOF::*; 10.33 -import SFIFO::*; 10.34 -import RWire::*; 10.35 - 10.36 -import Trace::*; 10.37 -import BFIFO::*; 10.38 -import MemTypes::*; 10.39 -import ProcTypes::*; 10.40 -import BRegFile::*; 10.41 -import BranchPred::*; 10.42 -//import PathTypes::*; This is only there to force the debugging 10.43 - 10.44 -//AWB includes 10.45 -`include "asim/provides/low_level_platform_interface.bsh" 10.46 -`include "asim/provides/soft_connections.bsh" 10.47 -`include "asim/provides/common_services.bsh" 10.48 - 10.49 -// Local includes 10.50 -//`include "asim/provides/processor_library.bsh" (included above directly) 10.51 -`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" 10.52 -`include "asim/provides/common_services.bsh" 10.53 -`include "asim/dict/STATS_PROCESSOR.bsh" 10.54 -`include "asim/provides/audio_pipe_types.bsh" 10.55 - 10.56 -// Local includes. Look for the correspondingly named .awb files 10.57 -// workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/ 10.58 -// to find the actual Bluespec files which are used to generate 10.59 -// these includes. These files are specific to this audio processing 10.60 -// pipeline 10.61 - 10.62 -`include "asim/provides/audio_pipe_types.bsh" 10.63 - 10.64 -//interface CPUToHost; 10.65 -// method Bit#(32) cpuToHost(int req); 10.66 -//endinterface 10.67 - 10.68 -interface Proc; 10.69 - 10.70 - // Interface from processor to caches 10.71 - interface Client#(DataReq,DataResp) dmem_client; 10.72 - interface Client#(InstReq,InstResp) imem_client; 10.73 - 10.74 - // Interface for enabling/disabling statistics on the rest of the core 10.75 - interface Get#(Bool) statsEn_get; 10.76 - 10.77 -// // Interface to host 10.78 -// interface CPUToHost tohost; 10.79 - 10.80 - // Interface to Audio Pipeline 10.81 - interface AudioOut audioOut; 10.82 - 10.83 -endinterface 10.84 - 10.85 -//The full interface for this is as below in the common file for audioProcessorTypes.bsv 10.86 -interface AudioOut; 10.87 - interface Get#(AudioProcessorUnit) audioSampleOutput; 10.88 -endinterface 10.89 - 10.90 -//interface AudioIn; 10.91 -// interface Put#(AudioProcessorUnit) audioSampleInput; 10.92 -//endinterface 10.93 - 10.94 -typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits); 10.95 - 10.96 -//----------------------------------------------------------- 10.97 -// Register file module 10.98 -//----------------------------------------------------------- 10.99 - 10.100 -interface BRFile; 10.101 - method Action wr( Rindx rindx, Bit#(32) data ); 10.102 - method Bit#(32) rd1( Rindx rindx ); 10.103 - method Bit#(32) rd2( Rindx rindx ); 10.104 -endinterface 10.105 - 10.106 -module mkBRFile( BRFile ); 10.107 - 10.108 - RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile(); 10.109 - 10.110 - method Action wr( Rindx rindx, Bit#(32) data ); 10.111 - rfile.upd( rindx, data ); 10.112 - endmethod 10.113 - 10.114 - method Bit#(32) rd1( Rindx rindx ); 10.115 - return ( rindx == 0 ) ? 0 : rfile.sub(rindx); 10.116 - endmethod 10.117 - 10.118 - method Bit#(32) rd2( Rindx rindx ); 10.119 - return ( rindx == 0 ) ? 0 : rfile.sub(rindx); 10.120 - endmethod 10.121 - 10.122 -endmodule 10.123 - 10.124 -//----------------------------------------------------------- 10.125 -// Helper functions 10.126 -//----------------------------------------------------------- 10.127 - 10.128 -function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 ); 10.129 - return zeroExtend( pack( signedLT(val1,val2) ) ); 10.130 -endfunction 10.131 - 10.132 -function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 ); 10.133 - return zeroExtend( pack( val1 < val2 ) ); 10.134 -endfunction 10.135 - 10.136 -function Bit#(32) rshft( Bit#(32) val ); 10.137 - return zeroExtend(val[4:0]); 10.138 -endfunction 10.139 - 10.140 - 10.141 -//----------------------------------------------------------- 10.142 -// Find funct for wbQ 10.143 -//----------------------------------------------------------- 10.144 -function Bool findwbf(Rindx fVal, WBResult cmpVal); 10.145 - case (cmpVal) matches 10.146 - tagged WB_ALU {data:.res, dest:.rd} : 10.147 - return (fVal == rd); 10.148 - tagged WB_Load .rd : 10.149 - return (fVal == rd); 10.150 - tagged WB_Store .st : 10.151 - return False; 10.152 - tagged WB_Host .x : 10.153 - return False; 10.154 - endcase 10.155 -endfunction 10.156 - 10.157 - 10.158 -//----------------------------------------------------------- 10.159 -// Stall funct for wbQ 10.160 -//----------------------------------------------------------- 10.161 -function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f); 10.162 - case (inst) matches 10.163 - // -- Memory Ops ------------------------------------------------ 10.164 - tagged LW .it : 10.165 - return f.find(it.rbase); 10.166 - tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} : 10.167 - return (f.find(addr) || f.find2(dreg)); 10.168 - 10.169 - // -- Simple Ops ------------------------------------------------ 10.170 - tagged ADDIU .it : return f.find(it.rsrc); 10.171 - tagged SLTI .it : return f.find(it.rsrc); 10.172 - tagged SLTIU .it : return f.find(it.rsrc); 10.173 - tagged ANDI .it : return f.find(it.rsrc); 10.174 - tagged ORI .it : return f.find(it.rsrc); 10.175 - tagged XORI .it : return f.find(it.rsrc); 10.176 - 10.177 - tagged LUI .it : return f.find(it.rdst); //this rds/wrs itself 10.178 - tagged SLL .it : return f.find(it.rsrc); 10.179 - tagged SRL .it : return f.find(it.rsrc); 10.180 - tagged SRA .it : return f.find(it.rsrc); 10.181 - tagged SLLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); 10.182 - tagged SRLV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); 10.183 - tagged SRAV .it : return (f.find(it.rsrc) || f.find(it.rshamt)); 10.184 - tagged ADDU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.185 - tagged SUBU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.186 - tagged AND .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.187 - tagged OR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.188 - tagged XOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.189 - tagged NOR .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.190 - tagged SLT .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.191 - tagged SLTU .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.192 - 10.193 - 10.194 - // -- Branches -------------------------------------------------- 10.195 - 10.196 - tagged BLEZ .it : return (f.find(it.rsrc)); 10.197 - tagged BGTZ .it : return (f.find(it.rsrc)); 10.198 - tagged BLTZ .it : return (f.find(it.rsrc)); 10.199 - tagged BGEZ .it : return (f.find(it.rsrc)); 10.200 - tagged BEQ .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.201 - tagged BNE .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2)); 10.202 - 10.203 - // -- Jumps ----------------------------------------------------- 10.204 - 10.205 - tagged J .it : return False; 10.206 - tagged JR .it : return f.find(it.rsrc); 10.207 - tagged JALR .it : return f.find(it.rsrc); 10.208 - tagged JAL .it : return False; 10.209 - 10.210 - // -- Cop0 ------------------------------------------------------ 10.211 - 10.212 - tagged MTC0 .it : return f.find(it.rsrc); 10.213 - tagged MFC0 .it : return False; 10.214 - 10.215 - // -- Illegal --------------------------------------------------- 10.216 - 10.217 - default : return False; 10.218 - 10.219 - endcase 10.220 -endfunction 10.221 -//----------------------------------------------------------- 10.222 -// Reference processor 10.223 -//----------------------------------------------------------- 10.224 - 10.225 - 10.226 -//(* doc = "synthesis attribute ram_style mkProc distributed;" *) 10.227 -//(* synthesize *) 10.228 - 10.229 -module [CONNECTED_MODULE] mkProc( Proc ); 10.230 - 10.231 - //----------------------------------------------------------- 10.232 - // Debug port 10.233 - 10.234 - ServerStub_AUDIOCORERRR server_stub <- mkServerStub_AUDIOCORERRR(); 10.235 - 10.236 - 10.237 - //----------------------------------------------------------- 10.238 - // State 10.239 - 10.240 - // Standard processor state 10.241 - 10.242 - Reg#(Addr) pc <- mkReg(32'h00001000); 10.243 - Reg#(Epoch) epoch <- mkReg(0); 10.244 - Reg#(Stage) stage <- mkReg(PCgen); 10.245 - BRFile rf <- mkBRFile; 10.246 - 10.247 - // Branch Prediction 10.248 - BranchPred bp <- mkBranchPred(); 10.249 - FIFO#(PCStat) execpc <- mkLFIFO(); 10.250 - 10.251 - // Pipelines 10.252 - FIFO#(PCStat) pcQ <-mkSizedFIFO(3); 10.253 - SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf); 10.254 - 10.255 - Reg#(Bit#(32)) cp0_tohost <- mkReg(0); 10.256 - Reg#(Bit#(32)) cp0_fromhost <- mkReg(0); 10.257 - Reg#(Bool) cp0_statsEn <- mkReg(False); 10.258 - 10.259 - // Memory request/response state 10.260 - 10.261 - FIFO#(InstReq) instReqQ <- mkBFIFO1(); 10.262 - FIFO#(InstResp) instRespQ <- mkFIFO(); 10.263 - 10.264 - FIFO#(DataReq) dataReqQ <- mkBFIFO1(); 10.265 - FIFO#(DataResp) dataRespQ <- mkFIFO(); 10.266 - 10.267 - // Audio I/O 10.268 - FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO; 10.269 - FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO; 10.270 - 10.271 - 10.272 - // Statistics state (2010) 10.273 -// Reg#(Stat) num_cycles <- mkReg(0); 10.274 -// Reg#(Stat) num_inst <- mkReg(0); 10.275 - 10.276 - //Or: 10.277 - // Statistics state 10.278 - STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT); 10.279 - STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT); 10.280 - 10.281 - //----------------------------------------------------------- 10.282 - // Rules 10.283 - 10.284 - (* descending_urgency = "exec, pcgen" *) 10.285 - rule pcgen; //( stage == PCgen ); 10.286 - let pc_plus4 = pc + 4; 10.287 - 10.288 - traceTiny("mkProc", "pc",pc); 10.289 - traceTiny("mkProc", "pcgen","P"); 10.290 - instReqQ.enq( LoadReq{ addr:pc, tag:epoch} ); 10.291 - 10.292 - let next_pc = bp.get(pc); 10.293 - if (next_pc matches tagged Valid .npc) 10.294 - begin 10.295 - pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch}); 10.296 - pc <= npc; 10.297 - end 10.298 - else 10.299 - begin 10.300 - pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch}); 10.301 - pc <= pc_plus4; 10.302 - end 10.303 - 10.304 - endrule 10.305 - 10.306 - rule discard (instRespQ.first() matches tagged LoadResp .ld 10.307 - &&& ld.tag != epoch); 10.308 - traceTiny("mkProc", "stage", "D"); 10.309 - instRespQ.deq(); 10.310 - endrule 10.311 - 10.312 - (* conflict_free = "exec, writeback" *) 10.313 - rule exec (instRespQ.first() matches tagged LoadResp.ld 10.314 - &&& (ld.tag == epoch) 10.315 - &&& unpack(ld.data) matches .inst 10.316 - &&& !stall(inst, wbQ)); 10.317 - 10.318 - // Some abbreviations 10.319 - let sext = signExtend; 10.320 - let zext = zeroExtend; 10.321 - let sra = signedShiftRight; 10.322 - 10.323 - // Get the instruction 10.324 - 10.325 - instRespQ.deq(); 10.326 - Instr inst 10.327 - = case ( instRespQ.first() ) matches 10.328 - tagged LoadResp .ld : return unpack(ld.data); 10.329 - tagged StoreResp .st : return ?; 10.330 - endcase; 10.331 - 10.332 - // Get the PC info 10.333 - let instrpc = pcQ.first().qpc; 10.334 - let pc_plus4 = instrpc + 4; 10.335 - 10.336 - Bool branchTaken = False; 10.337 - Addr newPC = pc_plus4; 10.338 - 10.339 - // Tracing 10.340 - traceTiny("mkProc", "exec","X"); 10.341 - traceTiny("mkProc", "exInstTiny",inst); 10.342 - traceFull("mkProc", "exInstFull",inst); 10.343 - 10.344 - case ( inst ) matches 10.345 - 10.346 - // -- Memory Ops ------------------------------------------------ 10.347 - 10.348 - tagged LW .it : 10.349 - begin 10.350 - Addr addr = rf.rd1(it.rbase) + sext(it.offset); 10.351 - dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } ); 10.352 - wbQ.enq(tagged WB_Load it.rdst); 10.353 - end 10.354 - 10.355 - tagged SW .it : 10.356 - begin 10.357 - Addr addr = rf.rd1(it.rbase) + sext(it.offset); 10.358 - dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } ); 10.359 - wbQ.enq(tagged WB_Store); 10.360 - end 10.361 - 10.362 - // -- Simple Ops ------------------------------------------------ 10.363 - 10.364 - tagged ADDIU .it : 10.365 - begin 10.366 - Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm); 10.367 - wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst}); 10.368 - end 10.369 - tagged SLTI .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )}); 10.370 - tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) }); 10.371 - tagged ANDI .it : 10.372 - begin 10.373 - Bit#(32) zext_it_imm = zext(it.imm); 10.374 - wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} ); 10.375 - end 10.376 - tagged ORI .it : 10.377 - begin 10.378 - Bit#(32) zext_it_imm = zext(it.imm); 10.379 - wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} ); 10.380 - end 10.381 - tagged XORI .it : 10.382 - begin 10.383 - Bit#(32) zext_it_imm = zext(it.imm); 10.384 - wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )}); 10.385 - end 10.386 - tagged LUI .it : 10.387 - begin 10.388 - Bit#(32) zext_it_imm = zext(it.imm); 10.389 - wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) }); 10.390 - end 10.391 - 10.392 - tagged SLL .it : 10.393 - begin 10.394 - Bit#(32) zext_it_shamt = zext(it.shamt); 10.395 - wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} ); 10.396 - end 10.397 - tagged SRL .it : 10.398 - begin 10.399 - Bit#(32) zext_it_shamt = zext(it.shamt); 10.400 - wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )}); 10.401 - end 10.402 - tagged SRA .it : 10.403 - begin 10.404 - Bit#(32) zext_it_shamt = zext(it.shamt); 10.405 - wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )}); 10.406 - end 10.407 - tagged SLLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )}); 10.408 - tagged SRLV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} ); 10.409 - tagged SRAV .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) }); 10.410 - tagged ADDU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} ); 10.411 - tagged SUBU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} ); 10.412 - tagged AND .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} ); 10.413 - tagged OR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} ); 10.414 - tagged XOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} ); 10.415 - tagged NOR .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} ); 10.416 - tagged SLT .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); 10.417 - tagged SLTU .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) }); 10.418 - 10.419 - // -- Branches -------------------------------------------------- 10.420 - 10.421 - tagged BLEZ .it : 10.422 - if ( signedLE( rf.rd1(it.rsrc), 0 ) ) 10.423 - begin 10.424 - newPC = pc_plus4 + (sext(it.offset) << 2); 10.425 - branchTaken = True; 10.426 - end 10.427 - 10.428 - tagged BGTZ .it : 10.429 - if ( signedGT( rf.rd1(it.rsrc), 0 ) ) 10.430 - begin 10.431 - newPC = pc_plus4 + (sext(it.offset) << 2); 10.432 - branchTaken = True; 10.433 - end 10.434 - 10.435 - tagged BLTZ .it : 10.436 - if ( signedLT( rf.rd1(it.rsrc), 0 ) ) 10.437 - begin 10.438 - newPC = pc_plus4 + (sext(it.offset) << 2); 10.439 - branchTaken = True; 10.440 - end 10.441 - 10.442 - tagged BGEZ .it : 10.443 - if ( signedGE( rf.rd1(it.rsrc), 0 ) ) 10.444 - begin 10.445 - newPC = pc_plus4 + (sext(it.offset) << 2); 10.446 - branchTaken = True; 10.447 - end 10.448 - 10.449 - tagged BEQ .it : 10.450 - if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) ) 10.451 - begin 10.452 - newPC = pc_plus4 + (sext(it.offset) << 2); 10.453 - branchTaken = True; 10.454 - end 10.455 - 10.456 - tagged BNE .it : 10.457 - if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) ) 10.458 - begin 10.459 - newPC = pc_plus4 + (sext(it.offset) << 2); 10.460 - branchTaken = True; 10.461 - end 10.462 - 10.463 - // -- Jumps ----------------------------------------------------- 10.464 - 10.465 - tagged J .it : 10.466 - begin 10.467 - newPC = { pc_plus4[31:28], it.target, 2'b0 }; 10.468 - branchTaken = True; 10.469 - end 10.470 - 10.471 - tagged JR .it : 10.472 - begin 10.473 - newPC = rf.rd1(it.rsrc); 10.474 - branchTaken = True; 10.475 - end 10.476 - 10.477 - tagged JAL .it : 10.478 - begin 10.479 - wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 }); 10.480 - newPC = { pc_plus4[31:28], it.target, 2'b0 }; 10.481 - branchTaken = True; 10.482 - end 10.483 - 10.484 - tagged JALR .it : 10.485 - begin 10.486 - wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 }); 10.487 - newPC = rf.rd1(it.rsrc); 10.488 - branchTaken = True; 10.489 - end 10.490 - 10.491 - // -- Cop0 ------------------------------------------------------ 10.492 - 10.493 - tagged MTC0 .it : 10.494 - begin 10.495 - case ( it.cop0dst ) 10.496 - 5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc))); 10.497 - 5'd21 : cp0_tohost <= truncate(rf.rd1(it.rsrc)); 10.498 - default : 10.499 - $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" ); 10.500 - endcase 10.501 - wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be. 10.502 - end 10.503 - 10.504 -//this is host stuff? 10.505 - tagged MFC0 .it : 10.506 - begin 10.507 - case ( it.cop0src ) 10.508 - // not actually an ALU instruction but don't have the format otherwise 10.509 - 5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) }); 10.510 - 5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost }); 10.511 - 5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost }); 10.512 - default : 10.513 - $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" ); 10.514 - endcase 10.515 - end 10.516 - 10.517 - // -- Illegal --------------------------------------------------- 10.518 - 10.519 - default : 10.520 - $display( " RTL-ERROR : %m : Illegal instruction !" ); 10.521 - 10.522 - endcase 10.523 - 10.524 -//evaluate branch prediction 10.525 - Addr ppc = pcQ.first().qnxtpc; //predicted branch 10.526 - if (ppc != newPC) //prediction wrong 10.527 - begin 10.528 - epoch <= pcQ.first().qepoch + 1; 10.529 - bp.upd(instrpc, newPC); //update branch predictor 10.530 - pcQ.clear(); 10.531 - pc <= newPC; 10.532 - end 10.533 - else 10.534 - pcQ.deq(); 10.535 - 10.536 - if ( cp0_statsEn ) 10.537 - num_inst.incr(); 10.538 - 10.539 - endrule 10.540 - 10.541 - rule writeback; // ( stage == Writeback ); 10.542 - traceTiny("mkProc", "writeback","W"); 10.543 - 10.544 - 10.545 - // get what to do off the writeback queue 10.546 - wbQ.deq(); 10.547 - case (wbQ.first()) matches 10.548 - tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res); 10.549 - tagged WB_Load .regWr : 10.550 - begin 10.551 - dataRespQ.deq(); 10.552 - if (dataRespQ.first() matches tagged LoadResp .ld) 10.553 - rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue? Duplicate? 10.554 - end 10.555 - tagged WB_Store : dataRespQ.deq(); 10.556 - tagged WB_Host .dat : noAction; 10.557 - endcase 10.558 - 10.559 - endrule 10.560 - 10.561 - rule inc_num_cycles; 10.562 - if ( cp0_statsEn ) 10.563 - num_cycles.incr(); 10.564 - endrule 10.565 - 10.566 -(* conservative_implicit_conditions *) 10.567 - rule handleCPUToHost; 10.568 - let req <- server_stub.acceptRequest_ReadCPUToHost(); 10.569 - case (req) 10.570 - 0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost); 10.571 - 1: server_stub.sendResponse_ReadCPUToHost(pc); 10.572 - 2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage))); 10.573 - endcase 10.574 - endrule 10.575 - 10.576 - // for now, we don't do anything. 10.577 - rule connectAudioReqResp; 10.578 - $display("FIR copies a data"); 10.579 - outAudioFifo.enq(inAudioFifo.first); 10.580 - outAudioFifo.deq; 10.581 - endrule 10.582 - 10.583 - // Server items & rules: 10.584 - 10.585 - rule feedInput; 10.586 - let command <- server_stub.acceptRequest_SendUnprocessedStream(); 10.587 - AudioProcessorControl ctrl = unpack(truncate(command.ctrl)); 10.588 - 10.589 - if(ctrl == EndOfFile) 10.590 - begin 10.591 - inAudioFifo.enq(tagged EndOfFile); 10.592 - end 10.593 - else 10.594 - begin 10.595 - inAudioFifo.enq(tagged Sample unpack(truncate(command.sample))); 10.596 - end 10.597 - endrule 10.598 - 10.599 - 10.600 - //----------------------------------------------------------- 10.601 - // Methods 10.602 - 10.603 - interface Client imem_client; 10.604 - interface Get request = toGet(instReqQ); 10.605 - interface Put response = toPut(instRespQ); 10.606 - endinterface 10.607 - 10.608 - interface Client dmem_client; 10.609 - interface Get request = toGet(dataReqQ); 10.610 - interface Put response = toPut(dataRespQ); 10.611 - endinterface 10.612 - 10.613 - interface Get statsEn_get = toGet(asReg(cp0_statsEn)); 10.614 - 10.615 -// interface CPUToHost tohost; 10.616 -// method Bit#(32) cpuToHost(int req); 10.617 -// return (case (req) 10.618 -// 0: cp0_tohost; 10.619 -// 1: pc; 10.620 -// 2: zeroExtend(pack(stage)); 10.621 -// endcase); 10.622 -// endmethod 10.623 -// endinterface 10.624 - 10.625 - interface AudioOut audio; 10.626 - interface audioSampleOutput = fifoToGet(outAudioFifo); 10.627 - endinterface 10.628 - 10.629 - 10.630 -endmodule 10.631 -
11.1 --- a/modules/bluespec/Pygar/core/audioCore.bsv~ Tue Apr 27 23:31:38 2010 -0400 11.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 11.3 @@ -1,80 +0,0 @@ 11.4 -// The MIT License 11.5 - 11.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 11.7 - 11.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 11.9 -// of this software and associated documentation files (the "Software"), to deal 11.10 -// in the Software without restriction, including without limitation the rights 11.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11.12 -// copies of the Software, and to permit persons to whom the Software is 11.13 -// furnished to do so, subject to the following conditions: 11.14 - 11.15 -// The above copyright notice and this permission notice shall be included in 11.16 -// all copies or substantial portions of the Software. 11.17 - 11.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 11.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 11.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 11.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 11.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 11.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 11.24 -// THE SOFTWARE. 11.25 - 11.26 -import Connectable::*; 11.27 -import GetPut::*; 11.28 -import ClientServer::*; 11.29 -import Processor::*; 11.30 -import MemArb::*; 11.31 -import MemTypes::*; 11.32 - 11.33 -//AWB includes 11.34 -`include "asim/provides/low_level_platform_interface.bsh" 11.35 -`include "asim/provides/soft_connections.bsh" 11.36 -`include "asim/provides/common_services.bsh" 11.37 - 11.38 -// Local includes 11.39 -`include "asim/provides/processor_library.bsh" 11.40 -`include "asim/provides/mem_arb.bsh" 11.41 -`include "asim/provides/instruction_cache.bsh" 11.42 -`include "asim/provides/data_cache.bsh" 11.43 -`include "asim/provides/processor.bsh" 11.44 - 11.45 -interface Core; 11.46 - 11.47 - // Interface from core to main memory 11.48 - interface Client#(MainMemReq,MainMemResp) mmem_client; 11.49 - 11.50 - interface AudioOut audio; 11.51 - 11.52 -endinterface 11.53 - 11.54 -interface AudioOut; 11.55 - // interface Put#(AudioProcessorUnit) sampleInput; 11.56 - interface Get#(AudioProcessorUnit) sampleOutput; 11.57 -endinterface 11.58 - 11.59 -module [CONNECTED_MODULE] mkCore( Core ); 11.60 - 11.61 - // Instantiate the modules 11.62 - 11.63 - Proc proc <- mkProc(); 11.64 - ICache#(InstReq,InstResp) icache <- mkInstCache(); 11.65 - DCache#(DataReq,DataResp) dcache <- mkDataCache(); 11.66 - MemArb marb <- mkMemArb(); 11.67 - 11.68 - // Internal connections 11.69 - 11.70 - mkConnection( proc.statsEn_get, icache.statsEn_put ); 11.71 - mkConnection( proc.statsEn_get, dcache.statsEn_put ); 11.72 - mkConnection( proc.imem_client, icache.proc_server ); 11.73 - mkConnection( proc.dmem_client, dcache.proc_server ); 11.74 - mkConnection( icache.mmem_client, marb.cache0_server ); 11.75 - mkConnection( dcache.mmem_client, marb.cache1_server ); 11.76 - 11.77 - // Methods 11.78 - 11.79 - interface mmem_client = marb.mmem_client; 11.80 - 11.81 - interface AudioOut audio = proc.audioOut; 11.82 - 11.83 -endmodule
12.1 --- a/modules/bluespec/Pygar/core/audioCorePipeline.bsv~ Tue Apr 27 23:31:38 2010 -0400 12.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 12.3 @@ -1,94 +0,0 @@ 12.4 -// The MIT License 12.5 - 12.6 -// Copyright (c) 2009 Massachusetts Institute of Technology 12.7 - 12.8 -// Permission is hereby granted, free of charge, to any person obtaining a copy 12.9 -// of this software and associated documentation files (the "Software"), to deal 12.10 -// in the Software without restriction, including without limitation the rights 12.11 -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12.12 -// copies of the Software, and to permit persons to whom the Software is 12.13 -// furnished to do so, subject to the following conditions: 12.14 - 12.15 -// The above copyright notice and this permission notice shall be included in 12.16 -// all copies or substantial portions of the Software. 12.17 - 12.18 -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 12.19 -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 12.20 -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 12.21 -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 12.22 -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 12.23 -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 12.24 -// THE SOFTWARE. 12.25 - 12.26 -// Author: Kermin Fleming kfleming@mit.edu 12.27 - 12.28 -import Connectable::*; 12.29 -import GetPut::*; 12.30 -import ClientServer::*; 12.31 -import FIFO::*; 12.32 - 12.33 -//AWB includes 12.34 -`include "asim/provides/low_level_platform_interface.bsh" 12.35 -`include "asim/provides/soft_connections.bsh" 12.36 -`include "asim/provides/common_services.bsh" 12.37 - 12.38 -//Local includes 12.39 -`include "asim/provides/audio_pipe_types.bsh" //provides Audio Pipeline interface 12.40 -`include "asim/provides/core.bsh" 12.41 - 12.42 -`include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh" 12.43 -`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh" 12.44 - 12.45 -module [CONNECTED_MODULE] mkConnectedApplication (); 12.46 - Core core <- mkCore; 12.47 - Reg#(int) cycle <- mkReg(0); 12.48 - 12.49 - //External memory 12.50 - // I'm not comfortable assuming that the memory subsystem is in order 12.51 - // So I'll insert a completion buffer here. 12.52 - ClientStub_AUDIOCORERRR client_stub <- mkClientStub_AUDIOCORERRR(); 12.53 - // Make this big enough so that several outstanding requests may be supported 12.54 - FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8); 12.55 - 12.56 - // this is for the tracing 12.57 - rule printCycles; 12.58 - cycle <= cycle+1; 12.59 - $fdisplay(stderr, " => Cycle = %d", cycle); 12.60 - endrule 12.61 - 12.62 - rule sendMemReq; 12.63 - let coreReq <- core.mmem_client.request.get; 12.64 - case (coreReq) matches 12.65 - tagged LoadReq .load: begin 12.66 - //Allocate ROB space 12.67 - client_stub.makeRequest_MemoryRequestLoad(load.addr); 12.68 - tags.enq(load.tag); 12.69 - end 12.70 - tagged StoreReq .store: begin 12.71 - client_stub.makeRequest_MemoryRequestStore(store.addr,store.data); 12.72 - end 12.73 - endcase 12.74 - endrule 12.75 - 12.76 - rule receiveMemResp; 12.77 - let memResp <- client_stub.getResponse_MemoryRequestLoad(); 12.78 - tags.deq; 12.79 - core.mmem_client.response.put(tagged LoadResp {data:memResp, 12.80 - tag: tags.first}); 12.81 - endrule 12.82 - 12.83 - // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together. 12.84 - 12.85 - rule feedOutput; 12.86 - let pipelineData <- core.sampleOutput.get(); 12.87 - AudioProcessorControl endOfFileTag = EndOfFile; 12.88 - AudioProcessorControl sampleTag = Data; 12.89 - 12.90 - case (pipelineData) matches 12.91 - tagged EndOfFile: client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?); 12.92 - tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)), 12.93 - zeroExtend(pack(sample))); 12.94 - endcase 12.95 - endrule 12.96 - 12.97 -endmodule
13.1 --- a/modules/bluespec/Pygar/core/audio_core.awb~ Tue Apr 27 23:31:38 2010 -0400 13.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 13.3 @@ -1,16 +0,0 @@ 13.4 -i%name Simple Audio Processor Core 13.5 -%desc Instantiates a processor, some caches, and a memory arbiter 13.6 - 13.7 -%provides core 13.8 - 13.9 -%requires mem_arb 13.10 -%requires instruction_cache 13.11 -%requires data_cache 13.12 -%requires processor 13.13 -%requires processor_library 13.14 - 13.15 -%attributes 6_375 13.16 - 13.17 -%public audioCore.bsv 13.18 - 13.19 -
14.1 --- a/modules/bluespec/Pygar/core/audio_core_pipe.awb~ Tue Apr 27 23:31:38 2010 -0400 14.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 14.3 @@ -1,15 +0,0 @@ 14.4 -%name audio core 14.5 -%desc Instantiates a soft core used for audio, wrapped in the audio pipeline interface 14.6 - 14.7 -%provides audio_pipeline 14.8 - 14.9 -%requires core 14.10 -%requires funcp_simulated_memory 14.11 -%requires funcp_base_types 14.12 -%requires hasim_common 14.13 - 14.14 - 14.15 -%attributes 6_375 14.16 - 14.17 -%public audioCorePipeline.bsv 14.18 -
15.1 --- a/modules/bluespec/Pygar/core/audio_core_systems.awb~ Tue Apr 27 23:31:38 2010 -0400 15.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 15.3 @@ -1,21 +0,0 @@ 15.4 -%name Single Processor Application 15.5 -%desc Top level processor. This module wraps a processor, which at its highest level is just a memory stream. 15.6 - 15.7 -%provides connected_application 15.8 - 15.9 -%requires core 15.10 -%requires funcp_simulated_memory 15.11 -%requires funcp_base_types 15.12 -%requires hasim_common 15.13 - 15.14 -%attributes 6_375 15.15 - 15.16 -%sources -t BSV -v PUBLIC ProcessorSystem.bsv 15.17 -%sources -t CPP -v PUBLIC ProcessorSystem.cpp 15.18 -%sources -t H -v PUBLIC ProcessorSystem.h 15.19 -%sources -t CPP -v PUBLIC ProcessorSystemRRR.cpp 15.20 -%sources -t H -v PUBLIC ProcessorSystemRRR.h 15.21 -%sources -t RRR -v PUBLIC ProcessorSystemRRR.rrr 15.22 - 15.23 -%param SYNTH_BOUNDARY mkConnectedApplication "name of synthesis boundary" 15.24 -
16.1 --- a/modules/bluespec/Pygar/core/audio_pipe_types.awb~ Tue Apr 27 23:31:38 2010 -0400 16.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 16.3 @@ -1,10 +0,0 @@ 16.4 -i%name Simple Audio Processor Core 16.5 -%desc Instantiates a processor, some caches, and a memory arbiter 16.6 - 16.7 -%provides audio_pipe_types 16.8 - 16.9 -%attributes 6_375 16.10 - 16.11 -%public AudioPipeTypes.bsv 16.12 - 16.13 -
17.1 --- a/modules/bluespec/Pygar/core/processor.awb~ Tue Apr 27 23:31:38 2010 -0400 17.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 17.3 @@ -1,13 +0,0 @@ 17.4 -%name 3-Stage Processor 17.5 -%desc 3-Stage Processor, one stage per cycle. 17.6 - 17.7 -%provides processor 17.8 - 17.9 -%attributes 6_375 17.10 - 17.11 -%public Processor.bsv ProcTypes.bsv 17.12 -%public Processor.dic 17.13 - 17.14 - 17.15 - 17.16 -