1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/modules/bluespec/Pygar/core/#AudioCoreSystem.cpp#	Tue Apr 27 09:03:28 2010 -0400
     1.3 @@ -0,0 +1,146 @@
     1.4 +#include <stdio.h>
     1.5 +#include <pthread.h>
     1.6 +#include <semaphore.h>
     1.7 +
     1.8 +#include "asim/provides/connected_application.h"
     1.9 +#include "asim/provides/stats_device.h"
    1.10 +//#include "asim/provides/SndfileWavUtil.h"
    1.11 +
    1.12 +//#include "asim/rrr/client_stub_AUDIOCORERRR.h"
    1.13 +
    1.14 +using namespace std;
    1.15 +
    1.16 +pthread_mutex_t CONNECTED_APPLICATION_CLASS::lock;
    1.17 +pthread_cond_t  CONNECTED_APPLICATION_CLASS::cond;
    1.18 +sem_t CONNECTED_APPLICATION_CLASS::throttle;
    1.19 +
    1.20 +// constructor
    1.21 +CONNECTED_APPLICATION_CLASS::CONNECTED_APPLICATION_CLASS(VIRTUAL_PLATFORM vp) :
    1.22 +    clientStub(new AUDIOCORERRR_CLIENT_STUB_CLASS(this))
    1.23 +{
    1.24 +}
    1.25 +
    1.26 +// destructor
    1.27 +CONNECTED_APPLICATION_CLASS::~CONNECTED_APPLICATION_CLASS()
    1.28 +{
    1.29 +}
    1.30 +
    1.31 +// init
    1.32 +void
    1.33 +CONNECTED_APPLICATION_CLASS::Init()
    1.34 +{
    1.35 +
    1.36 +  pthread_mutex_init(&lock, NULL);
    1.37 +  pthread_cond_init(&cond, NULL);
    1.38 +  sem_init(&throttle, 0, 64);
    1.39 +
    1.40 +  // enable stats 
    1.41 +  STATS_DEVICE_SERVER_CLASS::GetInstance()->SetupStats();
    1.42 +}
    1.43 +
    1.44 +void
    1.45 +CONNECTED_APPLICATION_CLASS::UpdateSemaphore()
    1.46 +{
    1.47 +  sem_post(&throttle);
    1.48 +}
    1.49 +
    1.50 +void
    1.51 +CONNECTED_APPLICATION_CLASS::EndSimulation()
    1.52 +{
    1.53 +  printf("EndSimulation Called\n");
    1.54 +  fflush(stdout);
    1.55 +  pthread_mutex_lock(&lock);
    1.56 +  // Do something about the race occuring here
    1.57 +  pthread_cond_signal(&cond); 
    1.58 +  pthread_mutex_unlock(&lock);
    1.59 +  printf("EndSimulation done\n");
    1.60 +  fflush(stdout);  
    1.61 +}
    1.62 +
    1.63 +// main
    1.64 +void
    1.65 +CONNECTED_APPLICATION_CLASS::Main()
    1.66 +{
    1.67 +  FILE *inputFile;
    1.68 +  UINT16 sample;
    1.69 +  
    1.70 +  // Convert input wav to pcm
    1.71 +  generate_pcm("input.wav","input.pcm");
    1.72 +
    1.73 +  //Send data to the machine here.
    1.74 +  inputFile = fopen("input.pcm","r");
    1.75 +  assert(inputFile);
    1.76 +
    1.77 +
    1.78 +  int count = 0;
    1.79 +
    1.80 +  printf("main: about to enter loop %d\n", count);  
    1.81 +
    1.82 +  while(fread(&sample, 2, 1, inputFile)) {
    1.83 +    if(count%1000 == 0)
    1.84 +      printf("main: %d\n", count);
    1.85 +    count++;
    1.86 +    sem_wait(&throttle);
    1.87 +    clientStub->SendUnprocessedStream(Data,(UINT32)sample);
    1.88 +  } 
    1.89 +
    1.90 +  printf("main: out of loop\n");
    1.91 +
    1.92 +  // Need to put lock here to prevent potential race condition
    1.93 +  pthread_mutex_lock(&lock);
    1.94 +  clientStub->SendUnprocessedStream(EndOfFile,0);
    1.95 +
    1.96 +  printf("main: wait for end of file\n");
    1.97 +
    1.98 +  pthread_cond_wait(&cond, &lock);
    1.99 +  pthread_mutex_unlock(&lock);
   1.100 +
   1.101 +  printf("main: lastt data out\n");
   1.102 +
   1.103 +  // Convert input wav to pcm
   1.104 +  generate_wav("out_hw.pcm","input.wav","out_hw.wav");
   1.105 +
   1.106 +  printf("generate wav done\n");
   1.107 +
   1.108 +  fflush(stdout);
   1.109 +  exit(0);
   1.110 +}
   1.111 +
   1.112 +/*    THIS IS THE CODE HANDLING FROM THE REGULAR SOFT-CORE
   1.113 +TO BE INCORPORATED 
   1.114 +// main
   1.115 +void
   1.116 +CONNECTED_APPLICATION_CLASS::Main()
   1.117 +{
   1.118 +  int sleepCount = 0;
   1.119 +  int result = 0;
   1.120 +
   1.121 +  fflush(stdout); 
   1.122 +
   1.123 +  while ((result = clientStub->ReadCPUToHost(0)) != 1) {
   1.124 +    sleep(1);
   1.125 +    //printf("System controller sleeps with result: %d\n", result);
   1.126 +    sleepCount++;
   1.127 +    if(sleepCount == 100) {
   1.128 +      printf("Failed to get response from hardware, bailing\n\n");
   1.129 +      printf("This means that either your hardware is hanging\n");
   1.130 +      printf("or that the software hasn't given it enough time\n");
   1.131 +      printf("to complete.  If you think it needs more time, then\n");
   1.132 +      printf("edit CONNECTED_APPLICATION_CLASS::Main() in ProcessorSystem.cpp\n");
   1.133 +      printf("(connected_application)\n");
   1.134 +      exit(0);
   1.135 +    }
   1.136 +  }
   1.137 + 
   1.138 +  if(result == 1) {
   1.139 +    printf("\n***PASSED***\n");
   1.140 +  }
   1.141 +
   1.142 +  // Dump the stats file
   1.143 +
   1.144 +  STATS_DEVICE_SERVER_CLASS::GetInstance()->DumpStats();
   1.145 +  STATS_DEVICE_SERVER_CLASS::GetInstance()->EmitFile();
   1.146 +
   1.147 +  fflush(stdout); 
   1.148 +  exit(0);
   1.149 +}*/

     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/modules/bluespec/Pygar/core/#audioCorePipeline.bsv#	Tue Apr 27 09:03:28 2010 -0400
     2.3 @@ -0,0 +1,94 @@
     2.4 +// The MIT License
     2.5 +
     2.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
     2.7 +
     2.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
     2.9 +// of this software and associated documentation files (the "Software"), to deal
    2.10 +// in the Software without restriction, including without limitation the rights
    2.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    2.12 +// copies of the Software, and to permit persons to whom the Software is
    2.13 +// furnished to do so, subject to the following conditions:
    2.14 +
    2.15 +// The above copyright notice and this permission notice shall be included in
    2.16 +// all copies or substantial portions of the Software.
    2.17 +
    2.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    2.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    2.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    2.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    2.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    2.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    2.24 +// THE SOFTWARE.
    2.25 +
    2.26 +// Author: Kermin Fleming kfleming@mit.edu
    2.27 +
    2.28 +import Connectable::*;
    2.29 +import GetPut::*;
    2.30 +import ClientServer::*;
    2.31 +import FIFO::*;
    2.32 +
    2.33 +//AWB includes
    2.34 +`include "asim/provides/low_level_platform_interface.bsh"
    2.35 +`include "asim/provides/soft_connections.bsh"
    2.36 +`include "asim/provides/common_services.bsh"
    2.37 +
    2.38 +//Local includes
    2.39 +`include "asim/provides/audio_pipe_types.bsh"  //provides Audio Pipeline interface
    2.40 +`include "asim/provides/core.bsh"
    2.41 +
    2.42 +`include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
    2.43 +`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
    2.44 +
    2.45 +module [CONNECTED_MODULE] mkConnectedApplication ();
    2.46 +   Core core <- mkCore;
    2.47 +   Reg#(int) cycle <- mkReg(0);
    2.48 +
    2.49 +  //External memory 
    2.50 +  // I'm not comfortable assuming that the memory subsystem is in order  
    2.51 +  // So I'll insert a completion buffer here.  
    2.52 +  ClientStub_AUDICORERRR client_stub <- mkClientStub_AUDIOCORERRR();   
    2.53 +  // Make this big enough so that several outstanding requests may be supported
    2.54 +  FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
    2.55 +
    2.56 +  // this is for the tracing
    2.57 +  rule printCycles;
    2.58 +    cycle <= cycle+1;
    2.59 +    $fdisplay(stderr, " => Cycle = %d", cycle);
    2.60 +  endrule
    2.61 +
    2.62 +  rule sendMemReq;
    2.63 +    let coreReq <- core.mmem_client.request.get;
    2.64 +    case (coreReq) matches 
    2.65 +      tagged LoadReq .load: begin
    2.66 +                              //Allocate ROB space
    2.67 +                              client_stub.makeRequest_MemoryRequestLoad(load.addr);
    2.68 +                              tags.enq(load.tag);
    2.69 +                            end
    2.70 +      tagged StoreReq .store: begin
    2.71 +                                client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
    2.72 +                              end
    2.73 +    endcase
    2.74 +  endrule
    2.75 +  
    2.76 +  rule receiveMemResp;
    2.77 +    let memResp <- client_stub.getResponse_MemoryRequestLoad();
    2.78 +    tags.deq;
    2.79 +    core.mmem_client.response.put(tagged LoadResp {data:memResp,
    2.80 +                                                   tag: tags.first});
    2.81 +  endrule
    2.82 +
    2.83 +  // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together.
    2.84 +
    2.85 +   rule feedOutput;
    2.86 +     let pipelineData <- core.sampleOutput.get();
    2.87 +     AudioProcessorControl endOfFileTag = EndOfFile;
    2.88 +     AudioProcessorControl sampleTag = Data;
    2.89 +
    2.90 +     case (pipelineData) matches
    2.91 +       tagged EndOfFile: client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
    2.92 +       tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)),
    2.93 +                                                                         zeroExtend(pack(sample)));
    2.94 +     endcase
    2.95 +   endrule
    2.96 +
    2.97 +endmodule

     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/modules/bluespec/Pygar/core/#olCore.bsv#	Tue Apr 27 09:03:28 2010 -0400
     3.3 @@ -0,0 +1,90 @@
     3.4 +// The MIT License
     3.5 +
     3.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
     3.7 +
     3.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
     3.9 +// of this software and associated documentation files (the "Software"), to deal
    3.10 +// in the Software without restriction, including without limitation the rights
    3.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    3.12 +// copies of the Software, and to permit persons to whom the Software is
    3.13 +// furnished to do so, subject to the following conditions:
    3.14 +
    3.15 +// The above copyright notice and this permission notice shall be included in
    3.16 +// all copies or substantial portions of the Software.
    3.17 +
    3.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    3.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    3.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
    3.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    3.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    3.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    3.24 +// THE SOFTWARE.
    3.25 +
    3.26 +import Connectable::*;
    3.27 +import GetPut::*;
    3.28 +import ClientServer::*;
    3.29 +
    3.30 +
    3.31 +import DataCacheBlocking::*;
    3.32 +import InstCacheBlocking::*;
    3.33 +import Processor::*;
    3.34 +import MemArb::*;
    3.35 +import MemTypes::*;
    3.36 +
    3.37 +`include "asim/provides/data_cache.bsh"
    3.38 +`include "asim/provides/instruction_cache.bsh"
    3.39 +
    3.40 +interface CoreStats;
    3.41 +  interface DCacheStats dcache;
    3.42 +  interface ICacheStats icache;
    3.43 +  interface ProcStats proc;
    3.44 +endinterface
    3.45 +
    3.46 +interface Core;
    3.47 +
    3.48 +  // Interface from core to main memory
    3.49 +  interface Client#(MainMemReq,MainMemResp) mmem_client;
    3.50 +
    3.51 +  // Statistics
    3.52 +  interface CoreStats stats;
    3.53 +
    3.54 +  // CPU to Host
    3.55 +  interface CPUToHost tohost;
    3.56 +
    3.57 +  // Interface to Audio Pipeline
    3.58 +  interface Audio audio;
    3.59 +
    3.60 +endinterface
    3.61 +
    3.62 +(* synthesize *)
    3.63 +module mkCore(Core);
    3.64 +
    3.65 +  // Instantiate the modules
    3.66 +  Proc proc <- mkProc();
    3.67 +  ICache#(InstReq,InstResp) icache <- mkInstCache();
    3.68 +  DCache#(DataReq,DataResp) dcache <- mkDataCache();
    3.69 +  MemArb marb <- mkMemArb();
    3.70 +
    3.71 +  // Internal connections
    3.72 +  mkConnection( proc.statsEn_get,   icache.statsEn_put );
    3.73 +  mkConnection( proc.statsEn_get,   dcache.statsEn_put );
    3.74 +  mkConnection( proc.imem_client,   icache.proc_server );
    3.75 +  mkConnection( proc.dmem_client,   dcache.proc_server );
    3.76 +  mkConnection( icache.mmem_client, marb.cache0_server );
    3.77 +  mkConnection( dcache.mmem_client, marb.cache1_server );
    3.78 +
    3.79 +  // Methods
    3.80 +  interface mmem_client = marb.mmem_client;
    3.81 +
    3.82 +  interface CoreStats stats;
    3.83 +    interface dcache = dcache.stats;
    3.84 +    interface icache = icache.stats;
    3.85 +    interface proc = proc.stats;
    3.86 +  endinterface
    3.87 +
    3.88 +  interface CPUToHost tohost = proc.tohost;
    3.89 +
    3.90 +  interface Audio audio = proc.audio;
    3.91 +	
    3.92 +endmodule
    3.93 +

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.cpp	Tue Apr 27 09:03:28 2010 -0400
     4.3 @@ -0,0 +1,118 @@
     4.4 +#include <cstdio>
     4.5 +#include <cstdlib>
     4.6 +#include <iostream>
     4.7 +#include <iomanip>
     4.8 +#include <stdio.h>
     4.9 +#include <sys/stat.h>
    4.10 +
    4.11 +#include "asim/rrr/service_ids.h"
    4.12 +
    4.13 +#include "asim/provides/connected_application.h"
    4.14 +
    4.15 +
    4.16 +
    4.17 +using namespace std;
    4.18 +
    4.19 +// ===== service instantiation =====
    4.20 +AUDIOCORERRR_SERVER_CLASS AUDIOCORERRR_SERVER_CLASS::instance;
    4.21 +
    4.22 +// constructor
    4.23 +AUDIOCORERRR_SERVER_CLASS::AUDIOCORERRR_SERVER_CLASS() :
    4.24 +  serverStub(new AUDICORERRR_SERVER_STUB_CLASS(this))
    4.25 +{
    4.26 +    // instantiate stub
    4.27 +    printf("AUDIOCORERRR init called\n");
    4.28 +    outputFile = NULL;
    4.29 +    memory = NULL;
    4.30 +    fflush(stdout);
    4.31 +}
    4.32 +
    4.33 +// destructor
    4.34 +AUDIOCORERRR_SERVER_CLASS::~AUDIOCORERRR_SERVER_CLASS()
    4.35 +{
    4.36 +    Cleanup();
    4.37 +}
    4.38 +
    4.39 +// init
    4.40 +void
    4.41 +AUDIOCORERRR_SERVER_CLASS::Init(PLATFORMS_MODULE p)
    4.42 +{
    4.43 +    parent = p;
    4.44 +}
    4.45 +
    4.46 +// uninit
    4.47 +void
    4.48 +AUDIOCORERRR_SERVER_CLASS::Uninit()
    4.49 +{
    4.50 +    Cleanup();
    4.51 +}
    4.52 +
    4.53 +// cleanup
    4.54 +void
    4.55 +AUDIOCORERRR_SERVER_CLASS::Cleanup()
    4.56 +{
    4.57 +    delete serverStub;
    4.58 +}
    4.59 +
    4.60 +
    4.61 +//
    4.62 +// RRR service methods
    4.63 +//
    4.64 +
    4.65 +UINT32
    4.66 +AUDIOCORERRR_SERVER_CLASS::MemoryRequestLoad (UINT32 address)
    4.67 +{
    4.68 +  UINT32 returnVal;
    4.69 +  
    4.70 +  if(memory == NULL) {
    4.71 +    memory = new FUNCP_SIMULATED_MEMORY_CLASS();
    4.72 +  }
    4.73 +
    4.74 + 
    4.75 +  memory->Read(0,(UINT64) address, sizeof(UINT32), &returnVal); 
    4.76 +  return returnVal;
    4.77 +}
    4.78 +
    4.79 +void
    4.80 +AUDIOCORERRR_SERVER_CLASS::MemoryRequestStore (UINT32 address, UINT32 data)
    4.81 +{
    4.82 +  if(memory == NULL) {
    4.83 +    memory = new FUNCP_SIMULATED_MEMORY_CLASS();
    4.84 +  }
    4.85 +
    4.86 +  memory->Write(0,(UINT64) address, sizeof(UINT32), &data); 
    4.87 +
    4.88 +void
    4.89 +
    4.90 +AUDIOCORERRR_SERVER_CLASS::SendProcessedStream(UINT16 control, UINT16 data)
    4.91 +{
    4.92 +
    4.93 +  AudioProcessorControl audioProcessorControl = (AudioProcessorControl) control;
    4.94 +  switch(control) {
    4.95 +    case EndOfFile:
    4.96 +      if(outputFile != NULL) {
    4.97 +        fflush(outputFile);
    4.98 +        fclose(outputFile);
    4.99 +        outputFile = NULL;
   4.100 +      } else {
   4.101 +        outputFile = fopen("out_hw.pcm","w");
   4.102 +        assert(outputFile);
   4.103 +        fflush(outputFile);
   4.104 +        fclose(outputFile);
   4.105 +      }
   4.106 +
   4.107 +      // Long term this should be in the data portion.  But until I have code running, keep it here.
   4.108 +      CONNECTED_APPLICATION_CLASS::EndSimulation(); 
   4.109 +    break;
   4.110 +
   4.111 +    case Data:
   4.112 +      if(outputFile == NULL) {
   4.113 +        outputFile = fopen("out_hw.pcm","w");
   4.114 +        assert(outputFile);
   4.115 +      }
   4.116 +
   4.117 +      CONNECTED_APPLICATION_CLASS::UpdateSemaphore();  
   4.118 +      fwrite(&data, 2,1 , outputFile);
   4.119 +    break;
   4.120 +  }
   4.121 +}

     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.cpp~	Tue Apr 27 09:03:28 2010 -0400
     5.3 @@ -0,0 +1,118 @@
     5.4 +#include <cstdio>
     5.5 +#include <cstdlib>
     5.6 +#include <iostream>
     5.7 +#include <iomanip>
     5.8 +#include <stdio.h>
     5.9 +#include <sys/stat.h>
    5.10 +
    5.11 +#include "asim/rrr/service_ids.h"
    5.12 +
    5.13 +#include "asim/provides/connected_application.h"
    5.14 +
    5.15 +
    5.16 +
    5.17 +using namespace std;
    5.18 +
    5.19 +// ===== service instantiation =====
    5.20 +AUDIOCORERRR_SERVER_CLASS AUDIOCORERRR_SERVER_CLASS::instance;
    5.21 +
    5.22 +// constructor
    5.23 +AUDIOCORERRR_SERVER_CLASS::AUDIOCORERRR_SERVER_CLASS() :
    5.24 +  serverStub(new AUDICORERRR_SERVER_STUB_CLASS(this))
    5.25 +{
    5.26 +    // instantiate stub
    5.27 +    printf("AUDIOCORERRR init called\n");
    5.28 +    outputFile = NULL;
    5.29 +    memory = NULL;
    5.30 +    fflush(stdout);
    5.31 +}
    5.32 +
    5.33 +// destructor
    5.34 +AUDIOCORERRR_SERVER_CLASS::~PROCESSORSYSTEMRRR_SERVER_CLASS()
    5.35 +{
    5.36 +    Cleanup();
    5.37 +}
    5.38 +
    5.39 +// init
    5.40 +void
    5.41 +AUDIOCORERRR_SERVER_CLASS::Init(PLATFORMS_MODULE p)
    5.42 +{
    5.43 +    parent = p;
    5.44 +}
    5.45 +
    5.46 +// uninit
    5.47 +void
    5.48 +AUDIOCORERRR_SERVER_CLASS::Uninit()
    5.49 +{
    5.50 +    Cleanup();
    5.51 +}
    5.52 +
    5.53 +// cleanup
    5.54 +void
    5.55 +AUDIOCORERRR_SERVER_CLASS::Cleanup()
    5.56 +{
    5.57 +    delete serverStub;
    5.58 +}
    5.59 +
    5.60 +
    5.61 +//
    5.62 +// RRR service methods
    5.63 +//
    5.64 +
    5.65 +UINT32
    5.66 +AUDIOCORERRR_SERVER_CLASS::MemoryRequestLoad (UINT32 address)
    5.67 +{
    5.68 +  UINT32 returnVal;
    5.69 +  
    5.70 +  if(memory == NULL) {
    5.71 +    memory = new FUNCP_SIMULATED_MEMORY_CLASS();
    5.72 +  }
    5.73 +
    5.74 + 
    5.75 +  memory->Read(0,(UINT64) address, sizeof(UINT32), &returnVal); 
    5.76 +  return returnVal;
    5.77 +}
    5.78 +
    5.79 +void
    5.80 +AUDIOCORERRR_SERVER_CLASS::MemoryRequestStore (UINT32 address, UINT32 data)
    5.81 +{
    5.82 +  if(memory == NULL) {
    5.83 +    memory = new FUNCP_SIMULATED_MEMORY_CLASS();
    5.84 +  }
    5.85 +
    5.86 +  memory->Write(0,(UINT64) address, sizeof(UINT32), &data); 
    5.87 +
    5.88 +void
    5.89 +
    5.90 +AUDIOCORERRR_SERVER_CLASS::SendProcessedStream(UINT16 control, UINT16 data)
    5.91 +{
    5.92 +
    5.93 +  AudioProcessorControl audioProcessorControl = (AudioProcessorControl) control;
    5.94 +  switch(control) {
    5.95 +    case EndOfFile:
    5.96 +      if(outputFile != NULL) {
    5.97 +        fflush(outputFile);
    5.98 +        fclose(outputFile);
    5.99 +        outputFile = NULL;
   5.100 +      } else {
   5.101 +        outputFile = fopen("out_hw.pcm","w");
   5.102 +        assert(outputFile);
   5.103 +        fflush(outputFile);
   5.104 +        fclose(outputFile);
   5.105 +      }
   5.106 +
   5.107 +      // Long term this should be in the data portion.  But until I have code running, keep it here.
   5.108 +      CONNECTED_APPLICATION_CLASS::EndSimulation(); 
   5.109 +    break;
   5.110 +
   5.111 +    case Data:
   5.112 +      if(outputFile == NULL) {
   5.113 +        outputFile = fopen("out_hw.pcm","w");
   5.114 +        assert(outputFile);
   5.115 +      }
   5.116 +
   5.117 +      CONNECTED_APPLICATION_CLASS::UpdateSemaphore();  
   5.118 +      fwrite(&data, 2,1 , outputFile);
   5.119 +    break;
   5.120 +  }
   5.121 +}

     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.h	Tue Apr 27 09:03:28 2010 -0400
     6.3 @@ -0,0 +1,55 @@
     6.4 +
     6.5 +#ifndef _AUDIOCORERRR_
     6.6 +#define _AUDIOCORERRR_
     6.7 +
     6.8 +#include <stdio.h>
     6.9 +#include <sys/time.h>
    6.10 +
    6.11 +#include "asim/provides/low_level_platform_interface.h"
    6.12 +#include "asim/provides/funcp_simulated_memory.h"
    6.13 +#include "asim/provides/rrr.h"
    6.14 +
    6.15 +
    6.16 +
    6.17 +typedef class AUDIOCORERRR_SERVER_CLASS* AUDIOCORERRR_SERVER;
    6.18 +class AUDIOCORERRR_SERVER_CLASS: public RRR_SERVER_CLASS, public PLATFORMS_MODULE_CLASS
    6.19 +{
    6.20 +  private:
    6.21 +    // self-instantiation
    6.22 +    static AUDIOCORERRR_SERVER_CLASS instance;
    6.23 +    FUNCP_SIMULATED_MEMORY_CLASS *memory;   
    6.24 +
    6.25 + 
    6.26 +    // server stub
    6.27 +    RRR_SERVER_STUB serverStub;
    6.28 +
    6.29 +    int count;    
    6.30 +
    6.31 +  public:
    6.32 +    AUDIOCORERRR_SERVER_CLASS();
    6.33 +    ~AUDIOCORERRR_SERVER_CLASS();
    6.34 +
    6.35 +    // static methods
    6.36 +    static AUDIOCORERRR_SERVER GetInstance() { return &instance; }
    6.37 +
    6.38 +    // required RRR methods
    6.39 +    void Init(PLATFORMS_MODULE);
    6.40 +    void Uninit();
    6.41 +    void Cleanup();
    6.42 +
    6.43 +    //
    6.44 +    // RRR service methods
    6.45 +    //
    6.46 +
    6.47 +   UINT32 MemoryRequestLoad  (UINT32 address);
    6.48 +   void   MemoryRequestStore (UINT32 address, UINT32 data);
    6.49 +
    6.50 +   void SendProcessedStream(UINT16 control, UINT16 data0);
    6.51 +};
    6.52 +
    6.53 +
    6.54 +
    6.55 +// include server stub
    6.56 +#include "asim/rrr/server_stub_AUDIOCORERRR.h"
    6.57 +
    6.58 +#endif

     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.h~	Tue Apr 27 09:03:28 2010 -0400
     7.3 @@ -0,0 +1,53 @@
     7.4 +
     7.5 +#ifndef _PROCESSORSYSTEMRRR_
     7.6 +#define _PROCESSORSYSTEMRRR_
     7.7 +
     7.8 +#include <stdio.h>
     7.9 +#include <sys/time.h>
    7.10 +
    7.11 +#include "asim/provides/low_level_platform_interface.h"
    7.12 +#include "asim/provides/funcp_simulated_memory.h"
    7.13 +#include "asim/provides/rrr.h"
    7.14 +
    7.15 +
    7.16 +
    7.17 +typedef class PROCESSORSYSTEMRRR_SERVER_CLASS* PROCESSORSYSTEMRRR_SERVER;
    7.18 +class PROCESSORSYSTEMRRR_SERVER_CLASS: public RRR_SERVER_CLASS, public PLATFORMS_MODULE_CLASS
    7.19 +{
    7.20 +  private:
    7.21 +    // self-instantiation
    7.22 +    static PROCESSORSYSTEMRRR_SERVER_CLASS instance;
    7.23 +    FUNCP_SIMULATED_MEMORY_CLASS *memory;   
    7.24 +
    7.25 + 
    7.26 +    // server stub
    7.27 +    RRR_SERVER_STUB serverStub;
    7.28 +
    7.29 +    int count;    
    7.30 +
    7.31 +  public:
    7.32 +    PROCESSORSYSTEMRRR_SERVER_CLASS();
    7.33 +    ~PROCESSORSYSTEMRRR_SERVER_CLASS();
    7.34 +
    7.35 +    // static methods
    7.36 +    static PROCESSORSYSTEMRRR_SERVER GetInstance() { return &instance; }
    7.37 +
    7.38 +    // required RRR methods
    7.39 +    void Init(PLATFORMS_MODULE);
    7.40 +    void Uninit();
    7.41 +    void Cleanup();
    7.42 +
    7.43 +    //
    7.44 +    // RRR service methods
    7.45 +    //
    7.46 +
    7.47 +   UINT32 MemoryRequestLoad  (UINT32 address);
    7.48 +   void   MemoryRequestStore (UINT32 address, UINT32 data);
    7.49 +};
    7.50 +
    7.51 +
    7.52 +
    7.53 +// include server stub
    7.54 +#include "asim/rrr/server_stub_PROCESSORSYSTEMRRR.h"
    7.55 +
    7.56 +#endif

     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/modules/bluespec/Pygar/core/AudioCoreRRR.rrr	Tue Apr 27 09:03:28 2010 -0400
     8.3 @@ -0,0 +1,16 @@
     8.4 +service AUDIOCORERRR
     8.5 +{
     8.6 +    server hw (bsv, connection) <- sw (cpp, method)
     8.7 +    {
     8.8 +        method ReadCPUToHost  (out UINT32[32] regValue, in UINT32[32] dummy);
     8.9 +        method SendUnprocessedStream (in UINT32[32] ctrl, in UINT32[32] sample);
    8.10 +    };
    8.11 +
    8.12 +    server sw (cpp, method) <- hw (bsv, connection) 
    8.13 +    {
    8.14 +       method SendProcessedStream (in UINT32[32] ctrl, in UINT32[32] sample);
    8.15 +       method MemoryRequestLoad  (in UINT32[32] address, out UINT32[32] value);
    8.16 +       method MemoryRequestStore (in UINT32[32] address, in UINT32[32] value);
    8.17 +    };
    8.18 +
    8.19 + };

     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/modules/bluespec/Pygar/core/AudioCoreSystem.cpp	Tue Apr 27 09:03:28 2010 -0400
     9.3 @@ -0,0 +1,146 @@
     9.4 +#include <stdio.h>
     9.5 +#include <pthread.h>
     9.6 +#include <semaphore.h>
     9.7 +
     9.8 +#include "asim/provides/connected_application.h"
     9.9 +#include "asim/provides/stats_device.h"
    9.10 +//#include "asim/provides/SndfileWavUtil.h"
    9.11 +
    9.12 +#include "asim/rrr/client_stub_AUDIOCORERRR.h"
    9.13 +
    9.14 +using namespace std;
    9.15 +
    9.16 +pthread_mutex_t CONNECTED_APPLICATION_CLASS::lock;
    9.17 +pthread_cond_t  CONNECTED_APPLICATION_CLASS::cond;
    9.18 +sem_t CONNECTED_APPLICATION_CLASS::throttle;
    9.19 +
    9.20 +// constructor
    9.21 +CONNECTED_APPLICATION_CLASS::CONNECTED_APPLICATION_CLASS(VIRTUAL_PLATFORM vp) :
    9.22 +    clientStub(new AUDIOCORERRR_CLIENT_STUB_CLASS(this))
    9.23 +{
    9.24 +}
    9.25 +
    9.26 +// destructor
    9.27 +CONNECTED_APPLICATION_CLASS::~CONNECTED_APPLICATION_CLASS()
    9.28 +{
    9.29 +}
    9.30 +
    9.31 +// init
    9.32 +void
    9.33 +CONNECTED_APPLICATION_CLASS::Init()
    9.34 +{
    9.35 +
    9.36 +  pthread_mutex_init(&lock, NULL);
    9.37 +  pthread_cond_init(&cond, NULL);
    9.38 +  sem_init(&throttle, 0, 64);
    9.39 +
    9.40 +  // enable stats 
    9.41 +  STATS_DEVICE_SERVER_CLASS::GetInstance()->SetupStats();
    9.42 +}
    9.43 +
    9.44 +void
    9.45 +CONNECTED_APPLICATION_CLASS::UpdateSemaphore()
    9.46 +{
    9.47 +  sem_post(&throttle);
    9.48 +}
    9.49 +
    9.50 +void
    9.51 +CONNECTED_APPLICATION_CLASS::EndSimulation()
    9.52 +{
    9.53 +  printf("EndSimulation Called\n");
    9.54 +  fflush(stdout);
    9.55 +  pthread_mutex_lock(&lock);
    9.56 +  // Do something about the race occuring here
    9.57 +  pthread_cond_signal(&cond); 
    9.58 +  pthread_mutex_unlock(&lock);
    9.59 +  printf("EndSimulation done\n");
    9.60 +  fflush(stdout);  
    9.61 +}
    9.62 +
    9.63 +// main
    9.64 +void
    9.65 +CONNECTED_APPLICATION_CLASS::Main()
    9.66 +{
    9.67 +  FILE *inputFile;
    9.68 +  UINT16 sample;
    9.69 +  
    9.70 +  // Convert input wav to pcm
    9.71 +  generate_pcm("input.wav","input.pcm");
    9.72 +
    9.73 +  //Send data to the machine here.
    9.74 +  inputFile = fopen("input.pcm","r");
    9.75 +  assert(inputFile);
    9.76 +
    9.77 +
    9.78 +  int count = 0;
    9.79 +
    9.80 +  printf("main: about to enter loop %d\n", count);  
    9.81 +
    9.82 +  while(fread(&sample, 2, 1, inputFile)) {
    9.83 +    if(count%1000 == 0)
    9.84 +      printf("main: %d\n", count);
    9.85 +    count++;
    9.86 +    sem_wait(&throttle);
    9.87 +    clientStub->SendUnprocessedStream(Data,(UINT32)sample);
    9.88 +  } 
    9.89 +
    9.90 +  printf("main: out of loop\n");
    9.91 +
    9.92 +  // Need to put lock here to prevent potential race condition
    9.93 +  pthread_mutex_lock(&lock);
    9.94 +  clientStub->SendUnprocessedStream(EndOfFile,0);
    9.95 +
    9.96 +  printf("main: wait for end of file\n");
    9.97 +
    9.98 +  pthread_cond_wait(&cond, &lock);
    9.99 +  pthread_mutex_unlock(&lock);
   9.100 +
   9.101 +  printf("main: lastt data out\n");
   9.102 +
   9.103 +  // Convert input wav to pcm
   9.104 +  generate_wav("out_hw.pcm","input.wav","out_hw.wav");
   9.105 +
   9.106 +  printf("generate wav done\n");
   9.107 +
   9.108 +  fflush(stdout);
   9.109 +  exit(0);
   9.110 +}
   9.111 +
   9.112 +/*    THIS IS THE CODE HANDLING FROM THE REGULAR SOFT-CORE
   9.113 +TO BE INCORPORATED 
   9.114 +// main
   9.115 +void
   9.116 +CONNECTED_APPLICATION_CLASS::Main()
   9.117 +{
   9.118 +  int sleepCount = 0;
   9.119 +  int result = 0;
   9.120 +
   9.121 +  fflush(stdout); 
   9.122 +
   9.123 +  while ((result = clientStub->ReadCPUToHost(0)) != 1) {
   9.124 +    sleep(1);
   9.125 +    //printf("System controller sleeps with result: %d\n", result);
   9.126 +    sleepCount++;
   9.127 +    if(sleepCount == 100) {
   9.128 +      printf("Failed to get response from hardware, bailing\n\n");
   9.129 +      printf("This means that either your hardware is hanging\n");
   9.130 +      printf("or that the software hasn't given it enough time\n");
   9.131 +      printf("to complete.  If you think it needs more time, then\n");
   9.132 +      printf("edit CONNECTED_APPLICATION_CLASS::Main() in ProcessorSystem.cpp\n");
   9.133 +      printf("(connected_application)\n");
   9.134 +      exit(0);
   9.135 +    }
   9.136 +  }
   9.137 + 
   9.138 +  if(result == 1) {
   9.139 +    printf("\n***PASSED***\n");
   9.140 +  }
   9.141 +
   9.142 +  // Dump the stats file
   9.143 +
   9.144 +  STATS_DEVICE_SERVER_CLASS::GetInstance()->DumpStats();
   9.145 +  STATS_DEVICE_SERVER_CLASS::GetInstance()->EmitFile();
   9.146 +
   9.147 +  fflush(stdout); 
   9.148 +  exit(0);
   9.149 +}*/

    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/modules/bluespec/Pygar/core/AudioCoreSystem.cpp~	Tue Apr 27 09:03:28 2010 -0400
    10.3 @@ -0,0 +1,104 @@
    10.4 +#include <stdio.h>
    10.5 +#include <pthread.h>
    10.6 +#include <semaphore.h>
    10.7 +
    10.8 +#include "asim/provides/connected_application.h"
    10.9 +//#include "asim/provides/SndfileWavUtil.h"
   10.10 +
   10.11 +#include "asim/rrr/client_stub_AUDIOPROCESSORRRR.h"
   10.12 +
   10.13 +using namespace std;
   10.14 +
   10.15 +pthread_mutex_t CONNECTED_APPLICATION_CLASS::lock;
   10.16 +pthread_cond_t  CONNECTED_APPLICATION_CLASS::cond;
   10.17 +sem_t CONNECTED_APPLICATION_CLASS::throttle;
   10.18 +
   10.19 +// constructor
   10.20 +CONNECTED_APPLICATION_CLASS::CONNECTED_APPLICATION_CLASS(VIRTUAL_PLATFORM vp) :
   10.21 +    clientStub(new AUDIOPROCESSORRRR_CLIENT_STUB_CLASS(this))
   10.22 +{
   10.23 +}
   10.24 +
   10.25 +// destructor
   10.26 +CONNECTED_APPLICATION_CLASS::~CONNECTED_APPLICATION_CLASS()
   10.27 +{
   10.28 +}
   10.29 +
   10.30 +// init
   10.31 +void
   10.32 +CONNECTED_APPLICATION_CLASS::Init()
   10.33 +{
   10.34 +
   10.35 +  pthread_mutex_init(&lock, NULL);
   10.36 +  pthread_cond_init(&cond, NULL);
   10.37 +  sem_init(&throttle, 0, 64);
   10.38 +
   10.39 +}
   10.40 +
   10.41 +void
   10.42 +CONNECTED_APPLICATION_CLASS::UpdateSemaphore()
   10.43 +{
   10.44 +  sem_post(&throttle);
   10.45 +}
   10.46 +
   10.47 +void
   10.48 +CONNECTED_APPLICATION_CLASS::EndSimulation()
   10.49 +{
   10.50 +  printf("EndSimulation Called\n");
   10.51 +  fflush(stdout);
   10.52 +  pthread_mutex_lock(&lock);
   10.53 +  // Do something about the race occuring here
   10.54 +  pthread_cond_signal(&cond); 
   10.55 +  pthread_mutex_unlock(&lock);
   10.56 +  printf("EndSimulation done\n");
   10.57 +  fflush(stdout);  
   10.58 +}
   10.59 +
   10.60 +// main
   10.61 +void
   10.62 +CONNECTED_APPLICATION_CLASS::Main()
   10.63 +{
   10.64 +  FILE *inputFile;
   10.65 +  UINT16 sample;
   10.66 +  
   10.67 +  // Convert input wav to pcm
   10.68 +  generate_pcm("input.wav","input.pcm");
   10.69 +
   10.70 +  //Send data to the machine here.
   10.71 +  inputFile = fopen("input.pcm","r");
   10.72 +  assert(inputFile);
   10.73 +
   10.74 +
   10.75 +  int count = 0;
   10.76 +
   10.77 +  printf("main: about to enter loop %d\n", count);  
   10.78 +
   10.79 +  while(fread(&sample, 2, 1, inputFile)) {
   10.80 +    if(count%1000 == 0)
   10.81 +      printf("main: %d\n", count);
   10.82 +    count++;
   10.83 +    sem_wait(&throttle);
   10.84 +    clientStub->SendUnprocessedStream(Data,(UINT32)sample);
   10.85 +  } 
   10.86 +
   10.87 +  printf("main: out of loop\n");
   10.88 +
   10.89 +  // Need to put lock here to prevent potential race condition
   10.90 +  pthread_mutex_lock(&lock);
   10.91 +  clientStub->SendUnprocessedStream(EndOfFile,0);
   10.92 +
   10.93 +  printf("main: wait for end of file\n");
   10.94 +
   10.95 +  pthread_cond_wait(&cond, &lock);
   10.96 +  pthread_mutex_unlock(&lock);
   10.97 +
   10.98 +  printf("main: lastt data out\n");
   10.99 +
  10.100 +  // Convert input wav to pcm
  10.101 +  generate_wav("out_hw.pcm","input.wav","out_hw.wav");
  10.102 +
  10.103 +  printf("generate wav done\n");
  10.104 +
  10.105 +  fflush(stdout);
  10.106 +  exit(0);
  10.107 +}

    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/modules/bluespec/Pygar/core/AudioCoreSystem.h	Tue Apr 27 09:03:28 2010 -0400
    11.3 @@ -0,0 +1,56 @@
    11.4 +//
    11.5 +// INTEL CONFIDENTIAL
    11.6 +// Copyright (c) 2008 Intel Corp.  Recipient is granted a non-sublicensable 
    11.7 +// copyright license under Intel copyrights to copy and distribute this code 
    11.8 +// internally only. This code is provided "AS IS" with no support and with no 
    11.9 +// warranties of any kind, including warranties of MERCHANTABILITY,
   11.10 +// FITNESS FOR ANY PARTICULAR PURPOSE or INTELLECTUAL PROPERTY INFRINGEMENT. 
   11.11 +// By making any use of this code, Recipient agrees that no other licenses 
   11.12 +// to any Intel patents, trade secrets, copyrights or other intellectual 
   11.13 +// property rights are granted herein, and no other licenses shall arise by 
   11.14 +// estoppel, implication or by operation of law. Recipient accepts all risks 
   11.15 +// of use.
   11.16 +//
   11.17 +
   11.18 +// possibly use include paths to hide existing modules?
   11.19 +
   11.20 +#ifndef __AUDIO_CORE_CONNECTED_APPLICATION__
   11.21 +#define __AUDIO_CORE_CONNECTED_APPLICATION__
   11.22 +
   11.23 +#include <stdio.h>
   11.24 +#include <pthread.h>
   11.25 +#include <semaphore.h>
   11.26 +
   11.27 +#include "asim/provides/virtual_platform.h"
   11.28 +
   11.29 +#include "asim/rrr/client_stub_AUDIOCORERRRSYSTEM.h"
   11.30 +
   11.31 +typedef enum {
   11.32 +  EndOfFile = 0,
   11.33 +  Data = 1
   11.34 +} AudioProcessorControl; 
   11.35 +
   11.36 +
   11.37 +typedef class CONNECTED_APPLICATION_CLASS* CONNECTED_APPLICATION;
   11.38 +class CONNECTED_APPLICATION_CLASS : public PLATFORMS_MODULE_CLASS
   11.39 +{
   11.40 +  private:
   11.41 +    AUDIOCORERRR_CLIENT_STUB clientStub;
   11.42 +    static sem_t throttle;
   11.43 +    static pthread_mutex_t lock;
   11.44 +    static pthread_cond_t  cond;    
   11.45 +
   11.46 +  public:
   11.47 +    CONNECTED_APPLICATION_CLASS(VIRTUAL_PLATFORM vp);
   11.48 +    ~CONNECTED_APPLICATION_CLASS();
   11.49 +    static void EndSimulation();
   11.50 +    static void UpdateSemaphore();
   11.51 +
   11.52 +    // init
   11.53 +    void Init();
   11.54 +
   11.55 +    // main
   11.56 +    void Main();
   11.57 +};
   11.58 +
   11.59 +#endif

    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/modules/bluespec/Pygar/core/AudioCoreSystem.h~	Tue Apr 27 09:03:28 2010 -0400
    12.3 @@ -0,0 +1,56 @@
    12.4 +//
    12.5 +// INTEL CONFIDENTIAL
    12.6 +// Copyright (c) 2008 Intel Corp.  Recipient is granted a non-sublicensable 
    12.7 +// copyright license under Intel copyrights to copy and distribute this code 
    12.8 +// internally only. This code is provided "AS IS" with no support and with no 
    12.9 +// warranties of any kind, including warranties of MERCHANTABILITY,
   12.10 +// FITNESS FOR ANY PARTICULAR PURPOSE or INTELLECTUAL PROPERTY INFRINGEMENT. 
   12.11 +// By making any use of this code, Recipient agrees that no other licenses 
   12.12 +// to any Intel patents, trade secrets, copyrights or other intellectual 
   12.13 +// property rights are granted herein, and no other licenses shall arise by 
   12.14 +// estoppel, implication or by operation of law. Recipient accepts all risks 
   12.15 +// of use.
   12.16 +//
   12.17 +
   12.18 +// possibly use include paths to hide existing modules?
   12.19 +
   12.20 +#ifndef __AUDIO_CORE_CONNECTED_APPLICATION__
   12.21 +#define __AUDIO_CORE_CONNECTED_APPLICATION__
   12.22 +
   12.23 +#include <stdio.h>
   12.24 +#include <pthread.h>
   12.25 +#include <semaphore.h>
   12.26 +
   12.27 +#include "asim/provides/virtual_platform.h"
   12.28 +
   12.29 +#include "asim/rrr/client_stub_AUDIOPROCESSORRRR.h"
   12.30 +
   12.31 +typedef enum {
   12.32 +  EndOfFile = 0,
   12.33 +  Data = 1
   12.34 +} AudioProcessorControl; 
   12.35 +
   12.36 +
   12.37 +typedef class CONNECTED_APPLICATION_CLASS* CONNECTED_APPLICATION;
   12.38 +class CONNECTED_APPLICATION_CLASS : public PLATFORMS_MODULE_CLASS
   12.39 +{
   12.40 +  private:
   12.41 +    AUDIOPROCESSORRRR_CLIENT_STUB clientStub;
   12.42 +    static sem_t throttle;
   12.43 +    static pthread_mutex_t lock;
   12.44 +    static pthread_cond_t  cond;    
   12.45 +
   12.46 +  public:
   12.47 +    CONNECTED_APPLICATION_CLASS(VIRTUAL_PLATFORM vp);
   12.48 +    ~CONNECTED_APPLICATION_CLASS();
   12.49 +    static void EndSimulation();
   12.50 +    static void UpdateSemaphore();
   12.51 +
   12.52 +    // init
   12.53 +    void Init();
   12.54 +
   12.55 +    // main
   12.56 +    void Main();
   12.57 +};
   12.58 +
   12.59 +#endif

    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/modules/bluespec/Pygar/core/AudioPipeTypes.bsv	Tue Apr 27 09:03:28 2010 -0400
    13.3 @@ -0,0 +1,50 @@
    13.4 +
    13.5 +// The MIT License
    13.6 +
    13.7 +// Copyright (c) 2009 Massachusetts Institute of Technology
    13.8 +
    13.9 +// Permission is hereby granted, free of charge, to any person obtaining a copy
   13.10 +// of this software and associated documentation files (the "Software"), to deal
   13.11 +// in the Software without restriction, including without limitation the rights
   13.12 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   13.13 +// copies of the Software, and to permit persons to whom the Software is
   13.14 +// furnished to do so, subject to the following conditions:
   13.15 +
   13.16 +// The above copyright notice and this permission notice shall be included in
   13.17 +// all copies or substantial portions of the Software.
   13.18 +
   13.19 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   13.20 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   13.21 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   13.22 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   13.23 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   13.24 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   13.25 +// THE SOFTWARE.
   13.26 +
   13.27 +// Author: Ker
   13.28 +// min Fleming kfleming@mit.edu
   13.29 +
   13.30 +import Connectable::*;
   13.31 +import GetPut::*;
   13.32 +import ClientServer::*;
   13.33 +
   13.34 +typedef Int#(16) Sample;
   13.35 +
   13.36 +typedef enum {
   13.37 +  EndOfFile = 0,
   13.38 +  Data = 1
   13.39 +} AudioProcessorControl deriving (Bits,Eq);
   13.40 +
   13.41 +
   13.42 +typedef struct { 
   13.43 +  Sample left;
   13.44 +  Sample right;
   13.45 +} StereoSample deriving (Bits,Eq);
   13.46 +
   13.47 +typedef union tagged{
   13.48 + Sample Sample;
   13.49 + void EndOfFile;
   13.50 +} AudioProcessorUnit deriving (Bits,Eq);
   13.51 +
   13.52 +
   13.53 +

    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/modules/bluespec/Pygar/core/AudioPipeTypes.bsv~	Tue Apr 27 09:03:28 2010 -0400
    14.3 @@ -0,0 +1,53 @@
    14.4 +
    14.5 +// The MIT License
    14.6 +
    14.7 +// Copyright (c) 2009 Massachusetts Institute of Technology
    14.8 +
    14.9 +// Permission is hereby granted, free of charge, to any person obtaining a copy
   14.10 +// of this software and associated documentation files (the "Software"), to deal
   14.11 +// in the Software without restriction, including without limitation the rights
   14.12 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   14.13 +// copies of the Software, and to permit persons to whom the Software is
   14.14 +// furnished to do so, subject to the following conditions:
   14.15 +
   14.16 +// The above copyright notice and this permission notice shall be included in
   14.17 +// all copies or substantial portions of the Software.
   14.18 +
   14.19 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   14.20 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   14.21 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   14.22 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   14.23 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   14.24 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   14.25 +// THE SOFTWARE.
   14.26 +
   14.27 +// Author: Ker
   14.28 +// min Fleming kfleming@mit.edu
   14.29 +
   14.30 +import Connectable::*;
   14.31 +import GetPut::*;
   14.32 +import ClientServer::*;
   14.33 +
   14.34 +typedef Int#(16) Sample;
   14.35 +
   14.36 +typedef enum {
   14.37 +  EndOfFile = 0,
   14.38 +  Data = 1
   14.39 +} AudioProcessorControl deriving (Bits,Eq);
   14.40 +
   14.41 +
   14.42 +typedef struct { 
   14.43 +  Sample left;
   14.44 +  Sample right;
   14.45 +} StereoSample deriving (Bits,Eq);
   14.46 +
   14.47 +typedef union tagged{
   14.48 + Sample Sample;
   14.49 + void EndOfFile;
   14.50 +} AudioProcessorUnit deriving (Bits,Eq);
   14.51 +
   14.52 +interface AudioPipeline;
   14.53 +  interface Put#(AudioProcessorUnit) sampleInput;
   14.54 +  interface Get#(AudioProcessorUnit) sampleOutput;
   14.55 +endinterface
   14.56 +

    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/modules/bluespec/Pygar/core/Core.bsv~	Tue Apr 27 09:03:28 2010 -0400
    15.3 @@ -0,0 +1,81 @@
    15.4 +// The MIT License
    15.5 +
    15.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
    15.7 +
    15.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
    15.9 +// of this software and associated documentation files (the "Software"), to deal
   15.10 +// in the Software without restriction, including without limitation the rights
   15.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   15.12 +// copies of the Software, and to permit persons to whom the Software is
   15.13 +// furnished to do so, subject to the following conditions:
   15.14 +
   15.15 +// The above copyright notice and this permission notice shall be included in
   15.16 +// all copies or substantial portions of the Software.
   15.17 +
   15.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   15.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   15.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   15.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   15.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   15.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   15.24 +// THE SOFTWARE.
   15.25 +
   15.26 +import Connectable::*;
   15.27 +import GetPut::*;
   15.28 +import ClientServer::*;
   15.29 +
   15.30 +import DataCacheBlocking::*;
   15.31 +import InstCacheBlocking::*;
   15.32 +import Processor::*;
   15.33 +import MemArb::*;
   15.34 +import MemTypes::*;
   15.35 +
   15.36 +interface CoreStats;
   15.37 +  interface DCacheStats dcache;
   15.38 +  interface ICacheStats icache;
   15.39 +  interface ProcStats proc;
   15.40 +endinterface
   15.41 +
   15.42 +interface Core;
   15.43 +
   15.44 +  // Interface from core to main memory
   15.45 +  interface Client#(MainMemReq,MainMemResp) mmem_client;
   15.46 +
   15.47 +  // Statistics
   15.48 +  interface CoreStats stats;
   15.49 +
   15.50 +  // CPU to Host
   15.51 +  interface CPUToHost tohost;
   15.52 +
   15.53 +endinterface
   15.54 +
   15.55 +(* synthesize *)
   15.56 +module mkCore(Core);
   15.57 +
   15.58 +  // Instantiate the modules
   15.59 +  Proc proc <- mkProc();
   15.60 +  ICache#(InstReq,InstResp) icache <- mkInstCache();
   15.61 +  DCache#(DataReq,DataResp) dcache <- mkDataCache();
   15.62 +  MemArb marb <- mkMemArb();
   15.63 +
   15.64 +  // Internal connections
   15.65 +  mkConnection( proc.statsEn_get,   icache.statsEn_put );
   15.66 +  mkConnection( proc.statsEn_get,   dcache.statsEn_put );
   15.67 +  mkConnection( proc.imem_client,   icache.proc_server );
   15.68 +  mkConnection( proc.dmem_client,   dcache.proc_server );
   15.69 +  mkConnection( icache.mmem_client, marb.cache0_server );
   15.70 +  mkConnection( dcache.mmem_client, marb.cache1_server );
   15.71 +
   15.72 +  // Methods
   15.73 +  interface mmem_client = marb.mmem_client;
   15.74 +
   15.75 +  interface CoreStats stats;
   15.76 +    interface dcache = dcache.stats;
   15.77 +    interface icache = icache.stats;
   15.78 +    interface proc = proc.stats;
   15.79 +  endinterface
   15.80 +
   15.81 +  interface CPUToHost tohost = proc.tohost;
   15.82 +
   15.83 +endmodule
   15.84 +

    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/modules/bluespec/Pygar/core/ProcTypes.bsv~	Tue Apr 27 09:03:28 2010 -0400
    16.3 @@ -0,0 +1,375 @@
    16.4 +
    16.5 +import Trace::*;
    16.6 +
    16.7 +//----------------------------------------------------------------------
    16.8 +// Other typedefs
    16.9 +//----------------------------------------------------------------------
   16.10 +
   16.11 +typedef Bit#(32) Addr;
   16.12 +typedef Int#(18) Stat;
   16.13 +
   16.14 +//----------------------------------------------------------------------
   16.15 +// Basic instruction type
   16.16 +//----------------------------------------------------------------------
   16.17 +
   16.18 +typedef Bit#(5)  Rindx;
   16.19 +typedef Bit#(16) Simm;
   16.20 +typedef Bit#(16) Zimm;
   16.21 +typedef Bit#(8)  Epoch;
   16.22 +typedef Bit#(5)  Shamt;
   16.23 +typedef Bit#(26) Target;
   16.24 +typedef Bit#(5)  CP0indx;
   16.25 +typedef Bit#(32) Data;
   16.26 +
   16.27 +typedef enum
   16.28 +{
   16.29 + Taken,
   16.30 + NotTaken
   16.31 +}
   16.32 +  Direction
   16.33 +    deriving(Bits,Eq);   
   16.34 +
   16.35 +
   16.36 +//----------------------------------------------------------------------
   16.37 +// Pipeline typedefs
   16.38 +//----------------------------------------------------------------------
   16.39 +
   16.40 +typedef union tagged
   16.41 +{
   16.42 +  Tuple2#(Rindx,Data) ALUWB;
   16.43 +  Rindx               MemWB;
   16.44 +  Tuple2#(Rindx,Data) CoWB;
   16.45 +}     
   16.46 +  WritebackType
   16.47 +    deriving(Bits,Eq);	 
   16.48 +
   16.49 +////////////////////////
   16.50 +// I Add Writeback queue type
   16.51 +////////////
   16.52 +typedef union tagged
   16.53 +{
   16.54 +  struct {Bit#(32) data; Rindx dest; } WB_ALU;
   16.55 +  Bit#(32) WB_Host;
   16.56 +  Rindx WB_Load;
   16.57 +  void WB_Store;
   16.58 +} 
   16.59 +WBResult deriving(Eq, Bits);
   16.60 +
   16.61 +typedef struct{Addr qpc; Addr qnxtpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
   16.62 +//typedef struct{Addr qpc; Epoch qepoch;} PCStat deriving(Eq, Bits);
   16.63 +
   16.64 +typedef union tagged                
   16.65 +{
   16.66 +
   16.67 +  struct { Rindx rbase; Rindx rdst;  Simm offset;  } LW;
   16.68 +  struct { Rindx rbase; Rindx rsrc;  Simm offset;  } SW; 
   16.69 +
   16.70 +  struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } ADDIU;
   16.71 +  struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } SLTI;
   16.72 +  struct { Rindx rsrc;  Rindx rdst;  Simm imm;     } SLTIU;
   16.73 +  struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } ANDI;
   16.74 +  struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } ORI;
   16.75 +  struct { Rindx rsrc;  Rindx rdst;  Zimm imm;     } XORI;
   16.76 +  struct {              Rindx rdst;  Zimm imm;     } LUI;
   16.77 +
   16.78 +  struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SLL;
   16.79 +  struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SRL;
   16.80 +  struct { Rindx rsrc;  Rindx rdst;  Shamt shamt;  } SRA;
   16.81 +  struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SLLV;
   16.82 +  struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SRLV;
   16.83 +  struct { Rindx rsrc;  Rindx rdst;  Rindx rshamt; } SRAV;
   16.84 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } ADDU;
   16.85 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SUBU;
   16.86 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } AND;
   16.87 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } OR;
   16.88 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } XOR;
   16.89 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } NOR;
   16.90 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SLT;
   16.91 +  struct { Rindx rsrc1; Rindx rsrc2; Rindx rdst;   } SLTU;
   16.92 +
   16.93 +  struct { Target target;                          } J;
   16.94 +  struct { Target target;                          } JAL;
   16.95 +  struct { Rindx rsrc;                             } JR;
   16.96 +  struct { Rindx rsrc;  Rindx rdst;                } JALR;
   16.97 +  struct { Rindx rsrc1; Rindx rsrc2; Simm offset;  } BEQ;
   16.98 +  struct { Rindx rsrc1; Rindx rsrc2; Simm offset;  } BNE;
   16.99 +  struct { Rindx rsrc;  Simm offset;               } BLEZ;
  16.100 +  struct { Rindx rsrc;  Simm offset;               } BGTZ;
  16.101 +  struct { Rindx rsrc;  Simm offset;               } BLTZ;
  16.102 +  struct { Rindx rsrc;  Simm offset;               } BGEZ;
  16.103 +
  16.104 +  struct { Rindx rdst;  CP0indx cop0src;           } MFC0;
  16.105 +  struct { Rindx rsrc;  CP0indx cop0dst;           } MTC0; 
  16.106 +
  16.107 +  void                                               ILLEGAL;
  16.108 +
  16.109 +}
  16.110 +Instr deriving(Eq);
  16.111 +
  16.112 +//----------------------------------------------------------------------
  16.113 +// Pack and Unpack
  16.114 +//----------------------------------------------------------------------
  16.115 +
  16.116 +Bit#(6) opFUNC  = 6'b000000;  Bit#(6) fcSLL   = 6'b000000;
  16.117 +Bit#(6) opRT    = 6'b000001;  Bit#(6) fcSRL   = 6'b000010;
  16.118 +Bit#(6) opRS    = 6'b010000;  Bit#(6) fcSRA   = 6'b000011;
  16.119 +                              Bit#(6) fcSLLV  = 6'b000100;
  16.120 +Bit#(6) opLW    = 6'b100011;  Bit#(6) fcSRLV  = 6'b000110;
  16.121 +Bit#(6) opSW    = 6'b101011;  Bit#(6) fcSRAV  = 6'b000111;
  16.122 +                              Bit#(6) fcADDU  = 6'b100001;
  16.123 +Bit#(6) opADDIU = 6'b001001;  Bit#(6) fcSUBU  = 6'b100011;
  16.124 +Bit#(6) opSLTI  = 6'b001010;  Bit#(6) fcAND   = 6'b100100;
  16.125 +Bit#(6) opSLTIU = 6'b001011;  Bit#(6) fcOR    = 6'b100101;
  16.126 +Bit#(6) opANDI  = 6'b001100;  Bit#(6) fcXOR   = 6'b100110;
  16.127 +Bit#(6) opORI   = 6'b001101;  Bit#(6) fcNOR   = 6'b100111;
  16.128 +Bit#(6) opXORI  = 6'b001110;  Bit#(6) fcSLT   = 6'b101010;
  16.129 +Bit#(6) opLUI   = 6'b001111;  Bit#(6) fcSLTU  = 6'b101011;
  16.130 +
  16.131 +Bit#(6) opJ     = 6'b000010;
  16.132 +Bit#(6) opJAL   = 6'b000011;
  16.133 +Bit#(6) fcJR    = 6'b001000;
  16.134 +Bit#(6) fcJALR  = 6'b001001;
  16.135 +Bit#(6) opBEQ   = 6'b000100;
  16.136 +Bit#(6) opBNE   = 6'b000101;
  16.137 +Bit#(6) opBLEZ  = 6'b000110;
  16.138 +Bit#(6) opBGTZ  = 6'b000111;
  16.139 +Bit#(5) rtBLTZ  = 5'b00000;
  16.140 +Bit#(5) rtBGEZ  = 5'b00001;
  16.141 +
  16.142 +Bit#(5) rsMFC0  = 5'b00000;
  16.143 +Bit#(5) rsMTC0  = 5'b00100;
  16.144 +
  16.145 +instance Bits#(Instr,32);
  16.146 +
  16.147 +  // Pack Function
  16.148 +
  16.149 +  function Bit#(32) pack( Instr instr );
  16.150 +
  16.151 +    case ( instr ) matches
  16.152 +
  16.153 +      tagged LW    .it : return { opLW,    it.rbase, it.rdst,  it.offset };
  16.154 +      tagged SW    .it : return { opSW,    it.rbase, it.rsrc,  it.offset };
  16.155 +
  16.156 +      tagged ADDIU .it : return { opADDIU, it.rsrc,  it.rdst,  it.imm                      }; 
  16.157 +      tagged SLTI  .it : return { opSLTI,  it.rsrc,  it.rdst,  it.imm                      }; 
  16.158 +      tagged SLTIU .it : return { opSLTIU, it.rsrc,  it.rdst,  it.imm                      }; 
  16.159 +      tagged ANDI  .it : return { opANDI,  it.rsrc,  it.rdst,  it.imm                      }; 
  16.160 +      tagged ORI   .it : return { opORI,   it.rsrc,  it.rdst,  it.imm                      }; 
  16.161 +      tagged XORI  .it : return { opXORI,  it.rsrc,  it.rdst,  it.imm                      }; 
  16.162 +      tagged LUI   .it : return { opLUI,   5'b0,     it.rdst,  it.imm                      };
  16.163 +
  16.164 +      tagged SLL   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSLL  }; 
  16.165 +      tagged SRL   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSRL  }; 
  16.166 +      tagged SRA   .it : return { opFUNC,  5'b0,     it.rsrc,  it.rdst,   it.shamt, fcSRA  }; 
  16.167 +
  16.168 +      tagged SLLV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSLLV }; 
  16.169 +      tagged SRLV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSRLV }; 
  16.170 +      tagged SRAV  .it : return { opFUNC,  it.rshamt, it.rsrc, it.rdst,   5'b0,     fcSRAV }; 
  16.171 +
  16.172 +      tagged ADDU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcADDU }; 
  16.173 +      tagged SUBU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSUBU }; 
  16.174 +      tagged AND   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcAND  }; 
  16.175 +      tagged OR    .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcOR   }; 
  16.176 +      tagged XOR   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcXOR  }; 
  16.177 +      tagged NOR   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcNOR  }; 
  16.178 +      tagged SLT   .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSLT  }; 
  16.179 +      tagged SLTU  .it : return { opFUNC,  it.rsrc1, it.rsrc2, it.rdst,   5'b0,     fcSLTU }; 
  16.180 +
  16.181 +      tagged J     .it : return { opJ,     it.target                                       }; 
  16.182 +      tagged JAL   .it : return { opJAL,   it.target                                       }; 
  16.183 +      tagged JR    .it : return { opFUNC,  it.rsrc,  5'b0,     5'b0,      5'b0,     fcJR   };
  16.184 +      tagged JALR  .it : return { opFUNC,  it.rsrc,  5'b0,     it.rdst,   5'b0,     fcJALR };
  16.185 +      tagged BEQ   .it : return { opBEQ,   it.rsrc1, it.rsrc2, it.offset                   }; 
  16.186 +      tagged BNE   .it : return { opBNE,   it.rsrc1, it.rsrc2, it.offset                   }; 
  16.187 +      tagged BLEZ  .it : return { opBLEZ,  it.rsrc,  5'b0,     it.offset                   }; 
  16.188 +      tagged BGTZ  .it : return { opBGTZ,  it.rsrc,  5'b0,     it.offset                   }; 
  16.189 +      tagged BLTZ  .it : return { opRT,    it.rsrc,  rtBLTZ,   it.offset                   }; 
  16.190 +      tagged BGEZ  .it : return { opRT,    it.rsrc,  rtBGEZ,   it.offset                   }; 
  16.191 +
  16.192 +      tagged MFC0  .it : return { opRS,    rsMFC0,   it.rdst,  it.cop0src, 11'b0           }; 
  16.193 +      tagged MTC0  .it : return { opRS,    rsMTC0,   it.rsrc,  it.cop0dst, 11'b0           };  
  16.194 +
  16.195 +    endcase
  16.196 +
  16.197 +  endfunction
  16.198 +
  16.199 +  // Unpack Function
  16.200 +
  16.201 +  function Instr unpack( Bit#(32) instrBits );
  16.202 +
  16.203 +    let opcode = instrBits[ 31 : 26 ];
  16.204 +    let rs     = instrBits[ 25 : 21 ];
  16.205 +    let rt     = instrBits[ 20 : 16 ];
  16.206 +    let rd     = instrBits[ 15 : 11 ];
  16.207 +    let shamt  = instrBits[ 10 :  6 ];
  16.208 +    let funct  = instrBits[  5 :  0 ];
  16.209 +    let imm    = instrBits[ 15 :  0 ];
  16.210 +    let target = instrBits[ 25 :  0 ];
  16.211 +
  16.212 +    case ( opcode )
  16.213 +
  16.214 +      opLW        : return LW    { rbase:rs, rdst:rt,  offset:imm  };
  16.215 +      opSW        : return SW    { rbase:rs, rsrc:rt,  offset:imm  };
  16.216 +      opADDIU     : return ADDIU { rsrc:rs,  rdst:rt,  imm:imm     };
  16.217 +      opSLTI      : return SLTI  { rsrc:rs,  rdst:rt,  imm:imm     };
  16.218 +      opSLTIU     : return SLTIU { rsrc:rs,  rdst:rt,  imm:imm     };
  16.219 +      opANDI      : return ANDI  { rsrc:rs,  rdst:rt,  imm:imm     };
  16.220 +      opORI       : return ORI   { rsrc:rs,  rdst:rt,  imm:imm     };
  16.221 +      opXORI      : return XORI  { rsrc:rs,  rdst:rt,  imm:imm     };
  16.222 +      opLUI       : return LUI   {           rdst:rt,  imm:imm     };
  16.223 +      opJ         : return J     { target:target                   };
  16.224 +      opJAL       : return JAL   { target:target                   };
  16.225 +      opBEQ       : return BEQ   { rsrc1:rs, rsrc2:rt, offset:imm  };
  16.226 +      opBNE       : return BNE   { rsrc1:rs, rsrc2:rt, offset:imm  };
  16.227 +      opBLEZ      : return BLEZ  { rsrc:rs,  offset:imm            };
  16.228 +      opBGTZ      : return BGTZ  { rsrc:rs,  offset:imm            };
  16.229 +
  16.230 +      opFUNC  : 
  16.231 +        case ( funct )
  16.232 +          fcSLL   : return SLL   { rsrc:rt,  rdst:rd,  shamt:shamt };
  16.233 +          fcSRL   : return SRL   { rsrc:rt,  rdst:rd,  shamt:shamt };
  16.234 +          fcSRA   : return SRA   { rsrc:rt,  rdst:rd,  shamt:shamt };
  16.235 +          fcSLLV  : return SLLV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
  16.236 +          fcSRLV  : return SRLV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
  16.237 +          fcSRAV  : return SRAV  { rsrc:rt,  rdst:rd,  rshamt:rs   };
  16.238 +          fcADDU  : return ADDU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
  16.239 +          fcSUBU  : return SUBU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
  16.240 +          fcAND   : return AND   { rsrc1:rs, rsrc2:rt, rdst:rd     };
  16.241 +          fcOR    : return OR    { rsrc1:rs, rsrc2:rt, rdst:rd     };
  16.242 +          fcXOR   : return XOR   { rsrc1:rs, rsrc2:rt, rdst:rd     };
  16.243 +          fcNOR   : return NOR   { rsrc1:rs, rsrc2:rt, rdst:rd     };
  16.244 +          fcSLT   : return SLT   { rsrc1:rs, rsrc2:rt, rdst:rd     }; 
  16.245 +          fcSLTU  : return SLTU  { rsrc1:rs, rsrc2:rt, rdst:rd     };
  16.246 +          fcJR    : return JR    { rsrc:rs                         };
  16.247 +          fcJALR  : return JALR  { rsrc:rs,  rdst:rd               };
  16.248 +          default : return ILLEGAL;
  16.249 +        endcase
  16.250 +
  16.251 +      opRT : 
  16.252 +        case ( rt )
  16.253 +          rtBLTZ  : return BLTZ  { rsrc:rs,  offset:imm            };
  16.254 +          rtBGEZ  : return BGEZ  { rsrc:rs,  offset:imm            };
  16.255 +          default : return ILLEGAL;
  16.256 +        endcase
  16.257 +
  16.258 +      opRS : 
  16.259 +        case ( rs )
  16.260 +          rsMFC0  : return MFC0  { rdst:rt,  cop0src:rd            };
  16.261 +          rsMTC0  : return MTC0  { rsrc:rt,  cop0dst:rd            };
  16.262 +          default : return ILLEGAL;
  16.263 +        endcase
  16.264 +
  16.265 +      default : return ILLEGAL;
  16.266 +      
  16.267 +    endcase
  16.268 +
  16.269 +  endfunction
  16.270 +
  16.271 +endinstance
  16.272 +
  16.273 +//----------------------------------------------------------------------
  16.274 +// Trace
  16.275 +//----------------------------------------------------------------------
  16.276 +
  16.277 +instance Traceable#(Instr);
  16.278 +
  16.279 +  function Action traceTiny( String loc, String ttag, Instr inst );
  16.280 +    case ( inst ) matches
  16.281 +
  16.282 +      tagged LW    .it : $fdisplay(stderr,  " => %s:%s lw", loc,   ttag );
  16.283 +      tagged SW    .it : $fdisplay(stderr,  " => %s:%s sw", loc,   ttag );
  16.284 +
  16.285 +      tagged ADDIU .it : $fdisplay(stderr,  " => %s:%s addi", loc, ttag );
  16.286 +      tagged SLTI  .it : $fdisplay(stderr,  " => %s:%s sli", loc,  ttag );
  16.287 +      tagged SLTIU .it : $fdisplay(stderr,  " => %s:%s sliu", loc, ttag );
  16.288 +      tagged ANDI  .it : $fdisplay(stderr,  " => %s:%s andi", loc, ttag );
  16.289 +      tagged ORI   .it : $fdisplay(stderr,  " => %s:%s ori", loc,  ttag );
  16.290 +      tagged XORI  .it : $fdisplay(stderr,  " => %s:%s xori", loc, ttag );
  16.291 +      tagged LUI   .it : $fdisplay(stderr,  " => %s:%s lui", loc,  ttag );
  16.292 +                                          
  16.293 +      tagged SLL   .it : $fdisplay(stderr,  " => %s:%s sll", loc,  ttag );
  16.294 +      tagged SRL   .it : $fdisplay(stderr,  " => %s:%s srl", loc,  ttag );
  16.295 +      tagged SRA   .it : $fdisplay(stderr,  " => %s:%s sra", loc,  ttag );
  16.296 +      tagged SLLV  .it : $fdisplay(stderr,  " => %s:%s sllv", loc, ttag );
  16.297 +      tagged SRLV  .it : $fdisplay(stderr,  " => %s:%s srlv", loc, ttag );
  16.298 +      tagged SRAV  .it : $fdisplay(stderr,  " => %s:%s srav", loc, ttag );
  16.299 +                                          
  16.300 +      tagged ADDU  .it : $fdisplay(stderr,  " => %s:%s addu", loc, ttag );
  16.301 +      tagged SUBU  .it : $fdisplay(stderr,  " => %s:%s subu", loc, ttag );
  16.302 +      tagged AND   .it : $fdisplay(stderr,  " => %s:%s and", loc,  ttag );
  16.303 +      tagged OR    .it : $fdisplay(stderr,  " => %s:%s or", loc,   ttag );
  16.304 +      tagged XOR   .it : $fdisplay(stderr,  " => %s:%s xor", loc,  ttag );
  16.305 +      tagged NOR   .it : $fdisplay(stderr,  " => %s:%s nor", loc,  ttag );
  16.306 +      tagged SLT   .it : $fdisplay(stderr,  " => %s:%s slt", loc,  ttag );
  16.307 +      tagged SLTU  .it : $fdisplay(stderr,  " => %s:%s sltu", loc, ttag );
  16.308 +                                          
  16.309 +      tagged J     .it : $fdisplay(stderr,  " => %s:%s j", loc,    ttag );
  16.310 +      tagged JAL   .it : $fdisplay(stderr,  " => %s:%s jal", loc,  ttag );
  16.311 +      tagged JR    .it : $fdisplay(stderr,  " => %s:%s jr", loc,   ttag );
  16.312 +      tagged JALR  .it : $fdisplay(stderr,  " => %s:%s jalr", loc, ttag );
  16.313 +      tagged BEQ   .it : $fdisplay(stderr,  " => %s:%s beq", loc,  ttag );
  16.314 +      tagged BNE   .it : $fdisplay(stderr,  " => %s:%s bne", loc,  ttag );
  16.315 +      tagged BLEZ  .it : $fdisplay(stderr,  " => %s:%s blez", loc, ttag );
  16.316 +      tagged BGTZ  .it : $fdisplay(stderr,  " => %s:%s bgtz", loc, ttag );
  16.317 +      tagged BLTZ  .it : $fdisplay(stderr,  " => %s:%s bltz", loc, ttag );
  16.318 +      tagged BGEZ  .it : $fdisplay(stderr,  " => %s:%s bgez", loc, ttag );
  16.319 +                                           
  16.320 +      tagged MFC0  .it : $fdisplay(stderr,  " => %s:%s mfc0", loc, ttag );
  16.321 +      tagged MTC0  .it : $fdisplay(stderr,  " => %s:%s mtc0", loc, ttag );
  16.322 +
  16.323 +      tagged ILLEGAL   : $fdisplay(stderr,  " => %s:%s ill", loc,  ttag );
  16.324 +
  16.325 +    endcase
  16.326 +  endfunction
  16.327 +
  16.328 +  function Action traceFull( String loc, String ttag, Instr inst );
  16.329 +    case ( inst ) matches
  16.330 +
  16.331 +      tagged LW    .it : $fdisplay(stderr,  " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase );
  16.332 +      tagged SW    .it : $fdisplay(stderr,  " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase );
  16.333 +
  16.334 +      tagged ADDIU .it : $fdisplay(stderr,  " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
  16.335 +      tagged SLTI  .it : $fdisplay(stderr,  " => %s:%s slti r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
  16.336 +      tagged SLTIU .it : $fdisplay(stderr,  " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm );
  16.337 +      tagged ANDI  .it : $fdisplay(stderr,  " => %s:%s andi r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
  16.338 +      tagged ORI   .it : $fdisplay(stderr,  " => %s:%s ori r%0d, r%0d, 0x%x", loc,   ttag, it.rdst, it.rsrc, it.imm );
  16.339 +      tagged XORI  .it : $fdisplay(stderr,  " => %s:%s xori r%0d, r%0d, 0x%x", loc,  ttag, it.rdst, it.rsrc, it.imm );
  16.340 +      tagged LUI   .it : $fdisplay(stderr,  " => %s:%s lui r%0d, 0x%x", loc,         ttag, it.rdst, it.imm );
  16.341 +                                      
  16.342 +      tagged SLL   .it : $fdisplay(stderr,  " => %s:%s sll r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
  16.343 +      tagged SRL   .it : $fdisplay(stderr,  " => %s:%s srl r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
  16.344 +      tagged SRA   .it : $fdisplay(stderr,  " => %s:%s sra r%0d, r%0d, %0d", loc,   ttag, it.rdst, it.rsrc, it.shamt );
  16.345 +      tagged SLLV  .it : $fdisplay(stderr,  " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
  16.346 +      tagged SRLV  .it : $fdisplay(stderr,  " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
  16.347 +      tagged SRAV  .it : $fdisplay(stderr,  " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt );
  16.348 +                                      
  16.349 +      tagged ADDU  .it : $fdisplay(stderr,  " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
  16.350 +      tagged SUBU  .it : $fdisplay(stderr,  " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
  16.351 +      tagged AND   .it : $fdisplay(stderr,  " => %s:%s and r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
  16.352 +      tagged OR    .it : $fdisplay(stderr,  " => %s:%s or r%0d, r%0d, r%0d", loc,   ttag, it.rdst, it.rsrc1, it.rsrc2 );
  16.353 +      tagged XOR   .it : $fdisplay(stderr,  " => %s:%s xor r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
  16.354 +      tagged NOR   .it : $fdisplay(stderr,  " => %s:%s nor r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
  16.355 +      tagged SLT   .it : $fdisplay(stderr,  " => %s:%s slt r%0d, r%0d, r%0d", loc,  ttag, it.rdst, it.rsrc1, it.rsrc2 );
  16.356 +      tagged SLTU  .it : $fdisplay(stderr,  " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 );
  16.357 +                                      
  16.358 +      tagged J     .it : $fdisplay(stderr,  " => %s:%s j 0x%x", loc,    ttag, it.target );
  16.359 +      tagged JAL   .it : $fdisplay(stderr,  " => %s:%s jal 0x%x", loc,  ttag, it.target );
  16.360 +      tagged JR    .it : $fdisplay(stderr,  " => %s:%s jr r%0d", loc,   ttag, it.rsrc );
  16.361 +      tagged JALR  .it : $fdisplay(stderr,  " => %s:%s jalr r%0d", loc, ttag, it.rsrc );
  16.362 +      tagged BEQ   .it : $fdisplay(stderr,  " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
  16.363 +      tagged BNE   .it : $fdisplay(stderr,  " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset );
  16.364 +      tagged BLEZ  .it : $fdisplay(stderr,  " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
  16.365 +      tagged BGTZ  .it : $fdisplay(stderr,  " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
  16.366 +      tagged BLTZ  .it : $fdisplay(stderr,  " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
  16.367 +      tagged BGEZ  .it : $fdisplay(stderr,  " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset );
  16.368 +                                      
  16.369 +      tagged MFC0  .it : $fdisplay(stderr,  " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src );
  16.370 +      tagged MTC0  .it : $fdisplay(stderr,  " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst );
  16.371 +
  16.372 +      tagged ILLEGAL   : $fdisplay(stderr,  " => %s:%s illegal instruction", loc, ttag );
  16.373 +
  16.374 +    endcase
  16.375 +  endfunction
  16.376 +
  16.377 +endinstance
  16.378 +

    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/modules/bluespec/Pygar/core/Processor.bsv~	Tue Apr 27 09:03:28 2010 -0400
    17.3 @@ -0,0 +1,628 @@
    17.4 +/// The MIT License
    17.5 +
    17.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
    17.7 +
    17.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
    17.9 +// of this software and associated documentation files (the "Software"), to deal
   17.10 +// in the Software without restriction, including without limitation the rights
   17.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   17.12 +// copies of the Software, and to permit persons to whom the Software is
   17.13 +// furnished to do so, subject to the following conditions:
   17.14 +
   17.15 +// The above copyright notice and this permission notice shall be included in
   17.16 +// all copies or substantial portions of the Software.
   17.17 +
   17.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   17.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   17.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   17.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   17.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   17.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   17.24 +// THE SOFTWARE.
   17.25 +
   17.26 +import Connectable::*;
   17.27 +import GetPut::*;
   17.28 +import ClientServer::*;
   17.29 +import RegFile::*;
   17.30 +
   17.31 +import FIFO::*;
   17.32 +import FIFOF::*;
   17.33 +import SFIFO::*;
   17.34 +import RWire::*;
   17.35 +
   17.36 +import Trace::*;
   17.37 +import BFIFO::*;
   17.38 +import MemTypes::*;
   17.39 +import ProcTypes::*;
   17.40 +import BRegFile::*;
   17.41 +import BranchPred::*;
   17.42 +//import PathTypes::*;  This is only there to force the debugging
   17.43 +
   17.44 +//AWB includes
   17.45 +`include "asim/provides/low_level_platform_interface.bsh"
   17.46 +`include "asim/provides/soft_connections.bsh"
   17.47 +`include "asim/provides/common_services.bsh"
   17.48 +
   17.49 +// Local includes
   17.50 +//`include "asim/provides/processor_library.bsh" (included above directly)
   17.51 +`include "asim/rrr/remote_server_stub_PROCESSORSYSTEMRRR.bsh"
   17.52 +`include "asim/provides/common_services.bsh"
   17.53 +`include "asim/dict/STATS_PROCESSOR.bsh"
   17.54 +`include "asim/provides/audio_pipe_types.bsh"
   17.55 +
   17.56 +// Local includes. Look for the correspondingly named .awb files
   17.57 +// workspace/labs/src/mit-6.375/modules/bluespec/mit-6.375/common/
   17.58 +// to find the actual Bluespec files which are used to generate
   17.59 +// these includes.  These files are specific to this audio processing
   17.60 +// pipeline
   17.61 +
   17.62 +`include "asim/provides/audio_processor_types.bsh"
   17.63 +
   17.64 +//interface CPUToHost;
   17.65 +//  method Bit#(32) cpuToHost(int req);
   17.66 +//endinterface
   17.67 +
   17.68 +interface Proc;
   17.69 +
   17.70 +  // Interface from processor to caches
   17.71 +  interface Client#(DataReq,DataResp) dmem_client;
   17.72 +  interface Client#(InstReq,InstResp) imem_client;
   17.73 +
   17.74 +  // Interface for enabling/disabling statistics on the rest of the core
   17.75 +  interface Get#(Bool) statsEn_get;
   17.76 +
   17.77 +//  // Interface to host
   17.78 +//  interface CPUToHost tohost;
   17.79 +
   17.80 +  // Interface to Audio Pipeline
   17.81 +  interface AudioOut audioOut;
   17.82 +	
   17.83 +endinterface
   17.84 +
   17.85 +//The full interface for this is as below in the common file for audioProcessorTypes.bsv
   17.86 +interface AudioOut;
   17.87 +  interface Get#(AudioProcessorUnit) audioSampleOutput;
   17.88 +endinterface
   17.89 +
   17.90 +//interface AudioIn;
   17.91 +//  interface Put#(AudioProcessorUnit) audioSampleInput;
   17.92 +//endinterface	
   17.93 +
   17.94 +typedef enum { PCgen, Exec, Writeback } Stage deriving(Eq,Bits);
   17.95 +
   17.96 +//-----------------------------------------------------------
   17.97 +// Register file module
   17.98 +//-----------------------------------------------------------
   17.99 +
  17.100 +interface BRFile;
  17.101 +   method Action   wr( Rindx rindx, Bit#(32) data );
  17.102 +   method Bit#(32) rd1( Rindx rindx );
  17.103 +   method Bit#(32) rd2( Rindx rindx );
  17.104 +endinterface
  17.105 +
  17.106 +module mkBRFile( BRFile );
  17.107 +   
  17.108 +   RegFile#(Rindx,Bit#(32)) rfile <- mkBRegFile();
  17.109 +   
  17.110 +   method Action wr( Rindx rindx, Bit#(32) data );
  17.111 +      rfile.upd( rindx, data );
  17.112 +   endmethod
  17.113 +   
  17.114 +   method Bit#(32) rd1( Rindx rindx );
  17.115 +      return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
  17.116 +   endmethod
  17.117 +   
  17.118 +   method Bit#(32) rd2( Rindx rindx );
  17.119 +      return ( rindx == 0 ) ? 0 : rfile.sub(rindx);
  17.120 +   endmethod
  17.121 +
  17.122 +endmodule
  17.123 +
  17.124 +//-----------------------------------------------------------
  17.125 +// Helper functions
  17.126 +//-----------------------------------------------------------
  17.127 +
  17.128 +function Bit#(32) slt( Bit#(32) val1, Bit#(32) val2 );
  17.129 +   return zeroExtend( pack( signedLT(val1,val2) ) );
  17.130 +endfunction
  17.131 +
  17.132 +function Bit#(32) sltu( Bit#(32) val1, Bit#(32) val2 );
  17.133 +   return zeroExtend( pack( val1 < val2 ) );
  17.134 +endfunction
  17.135 +
  17.136 +function Bit#(32) rshft( Bit#(32) val );
  17.137 +   return zeroExtend(val[4:0]);
  17.138 +endfunction
  17.139 +
  17.140 +
  17.141 +//-----------------------------------------------------------
  17.142 +// Find funct for wbQ
  17.143 +//-----------------------------------------------------------
  17.144 +function Bool findwbf(Rindx fVal, WBResult cmpVal);
  17.145 +  case (cmpVal) matches   
  17.146 +     tagged WB_ALU  {data:.res, dest:.rd} :
  17.147 +	return (fVal == rd);
  17.148 +     tagged WB_Load .rd  :
  17.149 +	return (fVal == rd);
  17.150 +     tagged WB_Store .st :
  17.151 +	return False;
  17.152 +     tagged WB_Host .x   :
  17.153 +	return False;
  17.154 +  endcase
  17.155 +endfunction
  17.156 +
  17.157 +     
  17.158 +//-----------------------------------------------------------
  17.159 +// Stall funct for wbQ
  17.160 +//-----------------------------------------------------------
  17.161 +function Bool stall(Instr inst, SFIFO#(WBResult, Rindx) f);
  17.162 +   case (inst) matches
  17.163 +      	 // -- Memory Ops ------------------------------------------------      
  17.164 +      tagged LW .it :
  17.165 +	 return f.find(it.rbase);
  17.166 +      tagged SW {rsrc:.dreg, rbase:.addr, offset:.o} :
  17.167 +	 return (f.find(addr) ||  f.find2(dreg));
  17.168 +
  17.169 +	 // -- Simple Ops ------------------------------------------------      
  17.170 +      tagged ADDIU .it : return f.find(it.rsrc);
  17.171 +      tagged SLTI  .it : return f.find(it.rsrc);
  17.172 +      tagged SLTIU .it : return f.find(it.rsrc);
  17.173 +      tagged ANDI  .it : return f.find(it.rsrc);
  17.174 +      tagged ORI   .it : return f.find(it.rsrc);
  17.175 +      tagged XORI  .it : return f.find(it.rsrc);
  17.176 +      
  17.177 +      tagged LUI   .it : return f.find(it.rdst);  //this rds/wrs itself
  17.178 +      tagged SLL   .it : return f.find(it.rsrc);
  17.179 +      tagged SRL   .it : return f.find(it.rsrc);
  17.180 +      tagged SRA   .it : return f.find(it.rsrc);
  17.181 +      tagged SLLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));
  17.182 +      tagged SRLV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));
  17.183 +      tagged SRAV  .it : return (f.find(it.rsrc) || f.find(it.rshamt));
  17.184 +      tagged ADDU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.185 +      tagged SUBU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.186 +      tagged AND   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.187 +      tagged OR    .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.188 +      tagged XOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.189 +      tagged NOR   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.190 +      tagged SLT   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.191 +      tagged SLTU  .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.192 +   
  17.193 +
  17.194 +      // -- Branches --------------------------------------------------
  17.195 +    
  17.196 +      tagged BLEZ  .it : return (f.find(it.rsrc));
  17.197 +      tagged BGTZ  .it : return (f.find(it.rsrc));
  17.198 +      tagged BLTZ  .it : return (f.find(it.rsrc));
  17.199 +      tagged BGEZ  .it : return (f.find(it.rsrc));
  17.200 +      tagged BEQ   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.201 +      tagged BNE   .it : return (f.find(it.rsrc1) || f.find2(it.rsrc2));
  17.202 +      
  17.203 +      // -- Jumps -----------------------------------------------------
  17.204 +      
  17.205 +      tagged J     .it : return False;
  17.206 +      tagged JR    .it : return f.find(it.rsrc);
  17.207 +      tagged JALR  .it : return f.find(it.rsrc);
  17.208 +      tagged JAL   .it : return False;
  17.209 +      
  17.210 +      // -- Cop0 ------------------------------------------------------
  17.211 +      
  17.212 +      tagged MTC0  .it : return f.find(it.rsrc);      
  17.213 +      tagged MFC0  .it : return False; 
  17.214 +
  17.215 +      // -- Illegal ---------------------------------------------------
  17.216 +
  17.217 +      default : return False;
  17.218 +
  17.219 +    endcase
  17.220 +endfunction
  17.221 +//-----------------------------------------------------------
  17.222 +// Reference processor
  17.223 +//-----------------------------------------------------------
  17.224 +
  17.225 +
  17.226 +//(* doc = "synthesis attribute ram_style mkProc distributed;" *)
  17.227 +//(* synthesize *)
  17.228 +
  17.229 +module  [CONNECTED_MODULE] mkProc( Proc );
  17.230 +
  17.231 +   //-----------------------------------------------------------
  17.232 +   // Debug port
  17.233 +   
  17.234 +   ServerStub_PROCESSORSYSTEMRRR server_stub <- mkServerStub_PROCESSORSYSTEMRRR();   
  17.235 +
  17.236 +   
  17.237 +   //-----------------------------------------------------------
  17.238 +   // State
  17.239 +
  17.240 +   // Standard processor state
  17.241 +   
  17.242 +   Reg#(Addr)  pc    <- mkReg(32'h00001000);
  17.243 +   Reg#(Epoch) epoch <- mkReg(0);
  17.244 +   Reg#(Stage) stage <- mkReg(PCgen);
  17.245 +   BRFile      rf    <- mkBRFile;
  17.246 +
  17.247 +   // Branch Prediction
  17.248 +   BranchPred               bp <- mkBranchPred();
  17.249 +   FIFO#(PCStat)        execpc <- mkLFIFO();
  17.250 +   
  17.251 +   // Pipelines
  17.252 +   FIFO#(PCStat)           pcQ <-mkSizedFIFO(3);
  17.253 +   SFIFO#(WBResult, Rindx) wbQ <-mkSFIFO(findwbf);
  17.254 +
  17.255 +   Reg#(Bit#(32)) cp0_tohost   <- mkReg(0);
  17.256 +   Reg#(Bit#(32)) cp0_fromhost <- mkReg(0);
  17.257 +   Reg#(Bool)     cp0_statsEn  <- mkReg(False);
  17.258 +
  17.259 +   // Memory request/response state
  17.260 +   
  17.261 +   FIFO#(InstReq)  instReqQ    <- mkBFIFO1();
  17.262 +   FIFO#(InstResp) instRespQ   <- mkFIFO();
  17.263 +
  17.264 +   FIFO#(DataReq)  dataReqQ    <- mkBFIFO1();
  17.265 +   FIFO#(DataResp) dataRespQ   <- mkFIFO();
  17.266 +
  17.267 +   // Audio I/O
  17.268 +   FIFO#(AudioProcessorUnit) inAudioFifo <- mkFIFO;
  17.269 +   FIFO#(AudioProcessorUnit) outAudioFifo <- mkFIFO;
  17.270 +
  17.271 +
  17.272 +   // Statistics state (2010)
  17.273 +//   Reg#(Stat) num_cycles <- mkReg(0);
  17.274 +//   Reg#(Stat) num_inst <- mkReg(0);
  17.275 +
  17.276 +   //Or:
  17.277 +   // Statistics state
  17.278 +   STAT num_cycles <- mkStatCounter(`STATS_PROCESSOR_CYCLE_COUNT);
  17.279 +   STAT num_inst <- mkStatCounter(`STATS_PROCESSOR_INST_COUNT);
  17.280 +
  17.281 +   //-----------------------------------------------------------
  17.282 +   // Rules
  17.283 +
  17.284 +   (* descending_urgency = "exec, pcgen" *)
  17.285 +   rule pcgen; //( stage == PCgen );
  17.286 +      let pc_plus4 = pc + 4;
  17.287 +
  17.288 +      traceTiny("mkProc", "pc",pc);
  17.289 +      traceTiny("mkProc", "pcgen","P");
  17.290 +      instReqQ.enq( LoadReq{ addr:pc, tag:epoch} );
  17.291 +      
  17.292 +      let next_pc = bp.get(pc);
  17.293 +      if (next_pc matches tagged Valid .npc) 
  17.294 +	begin
  17.295 +	   pcQ.enq(PCStat {qpc:pc, qnxtpc:npc, qepoch:epoch});
  17.296 +	   pc <= npc;
  17.297 +	end
  17.298 +     else
  17.299 +	 begin
  17.300 +	   pcQ.enq(PCStat {qpc:pc, qnxtpc:pc_plus4, qepoch:epoch});
  17.301 +	   pc <= pc_plus4;
  17.302 +	 end
  17.303 +      
  17.304 +   endrule
  17.305 +
  17.306 +   rule discard (instRespQ.first() matches tagged LoadResp .ld
  17.307 +					      &&& ld.tag != epoch);
  17.308 +      traceTiny("mkProc", "stage", "D");
  17.309 +      instRespQ.deq();
  17.310 +   endrule
  17.311 +
  17.312 +   (* conflict_free = "exec, writeback" *)		      
  17.313 +   rule exec (instRespQ.first() matches tagged LoadResp.ld
  17.314 +	      &&& (ld.tag == epoch)
  17.315 +	      &&& unpack(ld.data) matches .inst
  17.316 +              &&& !stall(inst, wbQ));
  17.317 +
  17.318 +      // Some abbreviations
  17.319 +      let sext = signExtend;
  17.320 +      let zext = zeroExtend;
  17.321 +      let sra  = signedShiftRight;
  17.322 +      
  17.323 +      // Get the instruction
  17.324 +      
  17.325 +      instRespQ.deq();
  17.326 +      Instr inst 
  17.327 +      = case ( instRespQ.first() ) matches
  17.328 +	   tagged LoadResp  .ld : return unpack(ld.data);
  17.329 +	   tagged StoreResp .st : return ?;
  17.330 +	endcase;
  17.331 +
  17.332 +      // Get the PC info
  17.333 +      let instrpc = pcQ.first().qpc;
  17.334 +      let pc_plus4 = instrpc + 4;
  17.335 +      
  17.336 +      Bool branchTaken = False;
  17.337 +      Addr newPC = pc_plus4;
  17.338 +
  17.339 +      // Tracing
  17.340 +      traceTiny("mkProc", "exec","X");
  17.341 +      traceTiny("mkProc", "exInstTiny",inst);
  17.342 +      traceFull("mkProc", "exInstFull",inst);
  17.343 +
  17.344 +      case ( inst ) matches
  17.345 +
  17.346 +	 // -- Memory Ops ------------------------------------------------      
  17.347 +
  17.348 +	 tagged LW .it : 
  17.349 +	    begin
  17.350 +               Addr addr = rf.rd1(it.rbase) + sext(it.offset);
  17.351 +               dataReqQ.enq( LoadReq{ addr:addr, tag:zeroExtend(it.rdst) } );
  17.352 +               wbQ.enq(tagged WB_Load it.rdst);
  17.353 +	    end
  17.354 +
  17.355 +	 tagged SW .it : 
  17.356 +	    begin
  17.357 +               Addr addr = rf.rd1(it.rbase) + sext(it.offset);
  17.358 +               dataReqQ.enq( StoreReq{ tag:0, addr:addr, data:rf.rd2(it.rsrc) } );
  17.359 +               wbQ.enq(tagged WB_Store);
  17.360 +	    end
  17.361 +
  17.362 +	 // -- Simple Ops ------------------------------------------------      
  17.363 +
  17.364 +	 tagged ADDIU .it : 
  17.365 +	    begin
  17.366 +	       Bit#(32) result = rf.rd1(it.rsrc) + sext(it.imm);
  17.367 +	       wbQ.enq(tagged WB_ALU {data:result, dest:it.rdst});
  17.368 +	    end
  17.369 +	 tagged SLTI  .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:slt( rf.rd1(it.rsrc), sext(it.imm) )});
  17.370 +	 tagged SLTIU .it : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:sltu( rf.rd1(it.rsrc), sext(it.imm) ) });
  17.371 +	 tagged ANDI  .it : 
  17.372 +	    begin
  17.373 +	       Bit#(32) zext_it_imm = zext(it.imm);
  17.374 +	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) & zext_it_imm)} );
  17.375 +	    end
  17.376 +	 tagged ORI   .it : 
  17.377 +	    begin
  17.378 +	       Bit#(32) zext_it_imm = zext(it.imm);
  17.379 +	       wbQ.enq(tagged WB_ALU {dest:it.rdst, data:(rf.rd1(it.rsrc) | zext_it_imm)} );
  17.380 +	    end
  17.381 +	 tagged XORI  .it : 
  17.382 +	    begin
  17.383 +	       Bit#(32) zext_it_imm = zext(it.imm);
  17.384 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) ^ zext_it_imm )});
  17.385 +	    end
  17.386 +	 tagged LUI   .it : 
  17.387 +	    begin
  17.388 +	       Bit#(32) zext_it_imm = zext(it.imm);
  17.389 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(zext_it_imm << 32'd16) });
  17.390 +	    end
  17.391 +	 
  17.392 +	 tagged SLL   .it : 
  17.393 +	    begin
  17.394 +	       Bit#(32) zext_it_shamt = zext(it.shamt);
  17.395 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << zext_it_shamt )} );
  17.396 +	    end
  17.397 +	 tagged SRL   .it : 
  17.398 +	    begin
  17.399 +	       Bit#(32) zext_it_shamt = zext(it.shamt);
  17.400 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> zext_it_shamt )});
  17.401 +	    end
  17.402 +	 tagged SRA   .it : 
  17.403 +	    begin
  17.404 +	       Bit#(32) zext_it_shamt = zext(it.shamt);
  17.405 +	       wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), zext_it_shamt )});
  17.406 +	    end
  17.407 +	 tagged SLLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) << rshft(rf.rd2(it.rshamt)) )});
  17.408 +	 tagged SRLV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc) >> rshft(rf.rd2(it.rshamt)) )} );
  17.409 +	 tagged SRAV  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sra( rf.rd1(it.rsrc), rshft(rf.rd2(it.rshamt)) ) });
  17.410 +	 tagged ADDU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) + rf.rd2(it.rsrc2) )} );
  17.411 +	 tagged SUBU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) - rf.rd2(it.rsrc2) )} );
  17.412 +	 tagged AND   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) & rf.rd2(it.rsrc2) )} );
  17.413 +	 tagged OR    .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2) )} );
  17.414 +	 tagged XOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(rf.rd1(it.rsrc1) ^ rf.rd2(it.rsrc2) )} );
  17.415 +	 tagged NOR   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:(~(rf.rd1(it.rsrc1) | rf.rd2(it.rsrc2)) )} );
  17.416 +	 tagged SLT   .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:slt( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
  17.417 +	 tagged SLTU  .it : wbQ.enq(tagged WB_ALU {dest: it.rdst, data:sltu( rf.rd1(it.rsrc1), rf.rd2(it.rsrc2) ) });
  17.418 +
  17.419 +	 // -- Branches --------------------------------------------------
  17.420 +
  17.421 +	 tagged BLEZ  .it : 
  17.422 +            if ( signedLE( rf.rd1(it.rsrc), 0 ) )
  17.423 +	       begin
  17.424 +		  newPC = pc_plus4 + (sext(it.offset) << 2);
  17.425 +		  branchTaken = True;
  17.426 +	       end
  17.427 +
  17.428 +	 tagged BGTZ  .it : 
  17.429 +            if ( signedGT( rf.rd1(it.rsrc), 0 ) ) 
  17.430 +               begin 
  17.431 +		  newPC = pc_plus4 + (sext(it.offset) << 2);
  17.432 +		  branchTaken = True;
  17.433 +	       end
  17.434 +
  17.435 +	 tagged BLTZ  .it : 
  17.436 +            if ( signedLT( rf.rd1(it.rsrc), 0 ) )
  17.437 +               begin 
  17.438 +		  newPC = pc_plus4 + (sext(it.offset) << 2);
  17.439 +		  branchTaken = True;
  17.440 +	       end
  17.441 +		  
  17.442 +	 tagged BGEZ  .it : 
  17.443 +            if ( signedGE( rf.rd1(it.rsrc), 0 ) )
  17.444 +               begin 
  17.445 +		  newPC = pc_plus4 + (sext(it.offset) << 2);		  
  17.446 +		  branchTaken = True;
  17.447 +	       end
  17.448 +
  17.449 +      tagged BEQ   .it : 
  17.450 +        if ( rf.rd1(it.rsrc1) == rf.rd2(it.rsrc2) )
  17.451 +          begin 
  17.452 +	     newPC = pc_plus4 + (sext(it.offset) << 2);
  17.453 +	     branchTaken = True;
  17.454 +	  end
  17.455 +
  17.456 +      tagged BNE   .it : 
  17.457 +        if ( rf.rd1(it.rsrc1) != rf.rd2(it.rsrc2) )
  17.458 +          begin 
  17.459 +	     newPC = pc_plus4 + (sext(it.offset) << 2);
  17.460 +	     branchTaken = True;
  17.461 +	  end
  17.462 +
  17.463 +      // -- Jumps -----------------------------------------------------
  17.464 +      
  17.465 +      tagged J     .it : 
  17.466 +        begin 
  17.467 +	   newPC = { pc_plus4[31:28], it.target, 2'b0 };
  17.468 +	   branchTaken = True;
  17.469 +	end
  17.470 +      
  17.471 +      tagged JR    .it : 
  17.472 +        begin 
  17.473 +	   newPC = rf.rd1(it.rsrc);
  17.474 +	   branchTaken = True;
  17.475 +	end
  17.476 +
  17.477 +      tagged JAL   .it : 
  17.478 +       begin
  17.479 +          wbQ.enq(tagged WB_ALU {dest:31, data:pc_plus4 });
  17.480 +          newPC = { pc_plus4[31:28], it.target, 2'b0 };		  
  17.481 +	  branchTaken = True;
  17.482 +       end
  17.483 +
  17.484 +      tagged JALR  .it : 
  17.485 +       begin
  17.486 +          wbQ.enq(tagged WB_ALU {dest:it.rdst, data:pc_plus4 });
  17.487 +          newPC = rf.rd1(it.rsrc);
  17.488 +	  branchTaken = True;
  17.489 +       end
  17.490 +
  17.491 +      // -- Cop0 ------------------------------------------------------
  17.492 +      
  17.493 +      tagged MTC0  .it : 
  17.494 +	 begin
  17.495 +            case ( it.cop0dst )
  17.496 +	       5'd10 : cp0_statsEn <= unpack(truncate(rf.rd1(it.rsrc)));
  17.497 +	       5'd21 : cp0_tohost  <= truncate(rf.rd1(it.rsrc));
  17.498 +	       default :
  17.499 +	       $display( " RTL-ERROR : %m : Illegal MTC0 cop0dst register!" );
  17.500 +	    endcase
  17.501 +	    wbQ.enq(tagged WB_Host 0); //no idea wwhat this actually should be.
  17.502 +	 end
  17.503 +
  17.504 +//this is host stuff?
  17.505 +      tagged MFC0  .it :
  17.506 +	 begin
  17.507 +            case ( it.cop0src )
  17.508 +	    // not actually an ALU instruction but don't have the format otherwise
  17.509 +               5'd10 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:zext(pack(cp0_statsEn)) });
  17.510 +               5'd20 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_fromhost });
  17.511 +               5'd21 : wbQ.enq(tagged WB_ALU {dest:it.rdst, data:cp0_tohost   });
  17.512 +              default : 
  17.513 +                $display( " RTL-ERROR : %m : Illegal MFC0 cop0src register!" );
  17.514 +            endcase
  17.515 +	end
  17.516 +
  17.517 +      // -- Illegal ---------------------------------------------------
  17.518 +
  17.519 +      default : 
  17.520 +        $display( " RTL-ERROR : %m : Illegal instruction !" );
  17.521 +
  17.522 +    endcase
  17.523 +
  17.524 +//evaluate branch prediction
  17.525 +     Addr ppc = pcQ.first().qnxtpc; //predicted branch
  17.526 +     if (ppc != newPC) //prediction wrong
  17.527 +       begin
  17.528 +	  epoch <= pcQ.first().qepoch + 1;
  17.529 +	  bp.upd(instrpc, newPC); //update branch predictor
  17.530 +	  pcQ.clear();
  17.531 +	  pc <= newPC;
  17.532 +       end
  17.533 +     else
  17.534 +	pcQ.deq();
  17.535 +
  17.536 +    if ( cp0_statsEn )
  17.537 +      num_inst.incr();
  17.538 +
  17.539 +  endrule
  17.540 +
  17.541 +  rule writeback; // ( stage == Writeback );
  17.542 +     traceTiny("mkProc", "writeback","W");
  17.543 +     
  17.544 +
  17.545 +    // get what to do off the writeback queue
  17.546 +     wbQ.deq();
  17.547 +     case (wbQ.first()) matches
  17.548 +	tagged WB_ALU {data:.res, dest:.rdst} : rf.wr(rdst, res);
  17.549 +	tagged WB_Load .regWr : 
  17.550 +	   begin
  17.551 +	      dataRespQ.deq();
  17.552 +	      if (dataRespQ.first() matches tagged LoadResp .ld)
  17.553 +		rf.wr(truncate(ld.tag), ld.data); // no need to use Rindx from queue?  Duplicate?
  17.554 +	   end
  17.555 +	tagged WB_Store : dataRespQ.deq();
  17.556 +	tagged WB_Host .dat : noAction;
  17.557 +     endcase
  17.558 +           
  17.559 +  endrule
  17.560 +
  17.561 +  rule inc_num_cycles;
  17.562 +    if ( cp0_statsEn )
  17.563 +      num_cycles.incr();
  17.564 +  endrule
  17.565 +
  17.566 +(* conservative_implicit_conditions *)
  17.567 +  rule handleCPUToHost;
  17.568 +   let req <- server_stub.acceptRequest_ReadCPUToHost();
  17.569 +    case (req)
  17.570 +    0: server_stub.sendResponse_ReadCPUToHost(cp0_tohost);
  17.571 +     1: server_stub.sendResponse_ReadCPUToHost(pc);
  17.572 +     2: server_stub.sendResponse_ReadCPUToHost(zeroExtend(pack(stage)));
  17.573 +    endcase
  17.574 +  endrule
  17.575 +
  17.576 + // for now, we don't do anything.
  17.577 +  rule connectAudioReqResp;
  17.578 +    $display("FIR copies a data");
  17.579 +    outAudioFifo.enq(inAudioFifo.first);
  17.580 +    outAudioFifo.deq;
  17.581 +  endrule
  17.582 +
  17.583 +  // Server items & rules:
  17.584 +   
  17.585 +   rule feedInput;
  17.586 +     let command <- server_stub.acceptRequest_SendUnprocessedStream();
  17.587 +     AudioProcessorControl ctrl = unpack(truncate(command.ctrl));
  17.588 +
  17.589 +     if(ctrl == EndOfFile)
  17.590 +	begin  
  17.591 +          inAudioFifo.enq(tagged EndOfFile);
  17.592 +       end
  17.593 +     else 
  17.594 +       begin
  17.595 +          inAudioFifo.enq(tagged Sample unpack(truncate(command.sample)));
  17.596 +       end
  17.597 +   endrule     
  17.598 +  
  17.599 + 
  17.600 +  //-----------------------------------------------------------
  17.601 +  // Methods
  17.602 +
  17.603 +  interface Client imem_client;
  17.604 +    interface Get request  = toGet(instReqQ);
  17.605 +    interface Put response = toPut(instRespQ);
  17.606 +  endinterface
  17.607 +
  17.608 +  interface Client dmem_client;
  17.609 +    interface Get request  = toGet(dataReqQ);
  17.610 +    interface Put response = toPut(dataRespQ);
  17.611 +  endinterface
  17.612 +
  17.613 +  interface Get statsEn_get = toGet(asReg(cp0_statsEn));
  17.614 +
  17.615 +//  interface CPUToHost tohost;
  17.616 +//    method Bit#(32) cpuToHost(int req);
  17.617 +//      return (case (req)
  17.618 +//       0: cp0_tohost;
  17.619 +//       1: pc;
  17.620 +//       2: zeroExtend(pack(stage));
  17.621 +//      endcase);
  17.622 +//    endmethod
  17.623 +//  endinterface
  17.624 +     
  17.625 +  interface AudioOut audio;
  17.626 +     interface audioSampleOutput = fifoToGet(outAudioFifo);
  17.627 +  endinterface
  17.628 +
  17.629 +
  17.630 +endmodule
  17.631 +

    18.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.2 +++ b/modules/bluespec/Pygar/core/SndfileWavUtil.cpp	Tue Apr 27 09:03:28 2010 -0400
    18.3 @@ -0,0 +1,125 @@
    18.4 +#include <stdlib.h>
    18.5 +#include <string.h>
    18.6 +#include <errno.h>
    18.7 +#include <math.h>
    18.8 +#include <sndfile.h>
    18.9 +#include "SndfileWavUtil.h"
   18.10 +
   18.11 +void
   18.12 +generate_wav(const char * pcmfilename, const char * samplewavfilename, const char * outputwavfilename)
   18.13 +{
   18.14 +  char outfilename[2048];
   18.15 +  SNDFILE * outfile ;
   18.16 +  SNDFILE * wavfile ;
   18.17 +  SNDFILE * pcmfile ;
   18.18 +  SF_INFO wavinfo ;
   18.19 +  SF_INFO pcminfo ;
   18.20 +  int buff;
   18.21 +  SF_INSTRUMENT inst ;
   18.22 +  
   18.23 +  memset (&wavinfo, 0, sizeof (wavinfo)) ;
   18.24 +
   18.25 +  
   18.26 +  wavfile = sf_open(samplewavfilename, SFM_READ, &wavinfo);
   18.27 +
   18.28 +  if (wavfile == NULL){      
   18.29 +    printf ("\nERROR : Not able to open wav file named '%s' : %s/\n", samplewavfilename, sf_strerror (NULL)) ;
   18.30 +    exit (1) ;
   18.31 +  } ;
   18.32 +
   18.33 +  printf("WAV format: %x\n", wavinfo.format);
   18.34 +
   18.35 +  if (!((wavinfo.format & SF_FORMAT_PCM_16) && (wavinfo.channels == 1) && 
   18.36 +        (wavinfo.format & SF_FORMAT_WAV))){
   18.37 +    printf("\nERROR : .wav file must be SF_FORMAT_PCM_16 in mono\n");
   18.38 +  }
   18.39 +
   18.40 +  pcminfo.format = SF_FORMAT_RAW | SF_FORMAT_PCM_16;
   18.41 +  pcminfo.samplerate = wavinfo.samplerate;
   18.42 +  pcminfo.channels = wavinfo.channels;
   18.43 +
   18.44 +  pcmfile = sf_open(pcmfilename, SFM_READ, &pcminfo);
   18.45 +
   18.46 +  if (pcmfile == NULL){      
   18.47 +    printf ("\nERROR : Not able to open pcm file named '%s' : %s/\n", pcmfilename, sf_strerror (NULL)) ;
   18.48 +    exit (1) ;
   18.49 +  } ;
   18.50 +
   18.51 +
   18.52 +
   18.53 +  outfile = sf_open(outputwavfilename, SFM_WRITE, &wavinfo);
   18.54 +
   18.55 +  memset (&inst, 0, sizeof (inst)) ;
   18.56 +
   18.57 +  for(int i = SF_STR_FIRST; i <= SF_STR_LAST; i = i + 1) { 
   18.58 +    const char * str =  sf_get_string(wavfile,i);
   18.59 +    if(str != NULL) {
   18.60 +      sf_set_string(outfile,i,str);
   18.61 +    }
   18.62 +  }
   18.63 +  
   18.64 +  if (outfile == NULL){      
   18.65 +    printf ("\nERROR : Not able to create wav file named '%s' : %s/\n", outfilename, sf_strerror (NULL)) ;
   18.66 +    exit (1) ;
   18.67 +  } ;
   18.68 +
   18.69 +  while(sf_read_int(pcmfile, &buff, 1) == 1){
   18.70 +    if(sf_write_int(outfile, &buff, 1) != 1){
   18.71 +      printf("\nERROR : unable to write to '%s' : %s/\n", outfilename, sf_strerror(NULL));
   18.72 +    }
   18.73 +  }
   18.74 +  
   18.75 +  sf_close (wavfile) ;
   18.76 +  sf_close (outfile) ;
   18.77 +  sf_close (pcmfile) ;
   18.78 +  
   18.79 +}
   18.80 +
   18.81 +
   18.82 +void
   18.83 +generate_pcm (const char * wavfilename, const char * pcmfilename)
   18.84 +{
   18.85 +	SNDFILE * wavfile ;
   18.86 +	SNDFILE * pcmfile ;
   18.87 +	SF_INFO wavinfo ;
   18.88 +	SF_INFO pcminfo ;
   18.89 +	int buff;
   18.90 +
   18.91 +	memset (&wavinfo, 0, sizeof (wavinfo)) ;
   18.92 +	memset (&pcminfo, 0, sizeof (pcminfo)) ;
   18.93 +
   18.94 +	wavfile = sf_open (wavfilename, SFM_READ, &wavinfo) ;
   18.95 +
   18.96 +	if (wavfile == NULL){      
   18.97 +	  printf ("\nERROR : Not able to open wav file named '%s' : %s/\n", wavfilename, sf_strerror (NULL)) ;
   18.98 +	  exit (1) ;
   18.99 +	} ;
  18.100 +
  18.101 +	pcminfo.format = SF_FORMAT_RAW | SF_FORMAT_PCM_16;
  18.102 +	pcminfo.samplerate = wavinfo.samplerate;
  18.103 +	pcminfo.channels = wavinfo.channels;
  18.104 +
  18.105 +	if ((!wavinfo.format & SF_FORMAT_PCM_16) || (!wavinfo.channels == 1)){
  18.106 +	  printf("\nERROR : .wav file must be SF_FORMAT_PCM_16 and mono\n");
  18.107 +	}
  18.108 +
  18.109 +	pcmfile = sf_open (pcmfilename, SFM_WRITE, &pcminfo) ;
  18.110 +
  18.111 +	if (pcmfile == NULL){      
  18.112 +	  printf ("\nERROR : Not able to create pcm file named '%s' : %s/\n", pcmfilename, sf_strerror (NULL)) ;
  18.113 +	  exit (1) ;
  18.114 +	} ;
  18.115 +	
  18.116 +	while(sf_read_int(wavfile, &buff, 1) == 1){
  18.117 +	  if(sf_write_int(pcmfile, &buff, 1) != 1){
  18.118 +	    printf("\nERROR : unable to write to '%s' : %s/\n", pcmfilename, sf_strerror(NULL));
  18.119 +	  }
  18.120 +	}
  18.121 +
  18.122 +	sf_close (wavfile) ;
  18.123 +	sf_close (pcmfile) ;
  18.124 +} 
  18.125 +
  18.126 +
  18.127 +
  18.128 +

    19.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.2 +++ b/modules/bluespec/Pygar/core/SndfileWavUtil.h	Tue Apr 27 09:03:28 2010 -0400
    19.3 @@ -0,0 +1,9 @@
    19.4 +#ifndef _SNDFILE_WAV_UTIL_
    19.5 +#define _SNDFILE_WAV_UTIL_
    19.6 +
    19.7 +int guess_direction (const char * filename1, const char * filename2) ;
    19.8 +int guess_major_format (const char * filename) ;
    19.9 +void generate_pcm(const char * wavfilename, const char * pcmfilename);
   19.10 +void generate_wav(const char * pcmfilename, const char * samplewavfilename, const char * outputwavfilename);
   19.11 +
   19.12 +#endif

    20.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.2 +++ b/modules/bluespec/Pygar/core/audioCore.bsv	Tue Apr 27 09:03:28 2010 -0400
    20.3 @@ -0,0 +1,80 @@
    20.4 +// The MIT License
    20.5 +
    20.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
    20.7 +
    20.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
    20.9 +// of this software and associated documentation files (the "Software"), to deal
   20.10 +// in the Software without restriction, including without limitation the rights
   20.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   20.12 +// copies of the Software, and to permit persons to whom the Software is
   20.13 +// furnished to do so, subject to the following conditions:
   20.14 +
   20.15 +// The above copyright notice and this permission notice shall be included in
   20.16 +// all copies or substantial portions of the Software.
   20.17 +
   20.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   20.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   20.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   20.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   20.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   20.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   20.24 +// THE SOFTWARE.
   20.25 +
   20.26 +import Connectable::*;
   20.27 +import GetPut::*;
   20.28 +import ClientServer::*;
   20.29 +import Processor::*;
   20.30 +import MemArb::*;
   20.31 +import MemTypes::*;
   20.32 +
   20.33 +//AWB includes
   20.34 +`include "asim/provides/low_level_platform_interface.bsh"
   20.35 +`include "asim/provides/soft_connections.bsh"
   20.36 +`include "asim/provides/common_services.bsh"
   20.37 +
   20.38 +// Local includes
   20.39 +`include "asim/provides/processor_library.bsh"
   20.40 +`include "asim/provides/mem_arb.bsh"
   20.41 +`include "asim/provides/instruction_cache.bsh"
   20.42 +`include "asim/provides/data_cache.bsh"
   20.43 +`include "asim/provides/processor.bsh"
   20.44 +
   20.45 +interface Core;
   20.46 +
   20.47 +  // Interface from core to main memory
   20.48 +   interface Client#(MainMemReq,MainMemResp) mmem_client;
   20.49 +
   20.50 +   interface AudioOut audio;
   20.51 +
   20.52 +endinterface
   20.53 +
   20.54 +interface AudioOut;
   20.55 + //     interface Put#(AudioProcessorUnit) sampleInput;
   20.56 +      interface Get#(AudioProcessorUnit) sampleOutput;
   20.57 +endinterface      
   20.58 +
   20.59 +module   [CONNECTED_MODULE]  mkCore( Core );
   20.60 +
   20.61 +  // Instantiate the modules
   20.62 +
   20.63 +  Proc proc <- mkProc();
   20.64 +  ICache#(InstReq,InstResp) icache <- mkInstCache();
   20.65 +  DCache#(DataReq,DataResp) dcache <- mkDataCache();
   20.66 +  MemArb marb <- mkMemArb();
   20.67 +
   20.68 +  // Internal connections
   20.69 +
   20.70 +  mkConnection( proc.statsEn_get,   icache.statsEn_put );
   20.71 +  mkConnection( proc.statsEn_get,   dcache.statsEn_put );
   20.72 +  mkConnection( proc.imem_client,   icache.proc_server );
   20.73 +  mkConnection( proc.dmem_client,   dcache.proc_server );
   20.74 +  mkConnection( icache.mmem_client, marb.cache0_server );
   20.75 +  mkConnection( dcache.mmem_client, marb.cache1_server );
   20.76 +
   20.77 +  // Methods
   20.78 +
   20.79 +   interface mmem_client = marb.mmem_client;
   20.80 +
   20.81 +   interface AudioOut audio = proc.audioOut;
   20.82 +
   20.83 +endmodule

    21.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.2 +++ b/modules/bluespec/Pygar/core/audioCore.bsv~	Tue Apr 27 09:03:28 2010 -0400
    21.3 @@ -0,0 +1,84 @@
    21.4 +// The MIT License
    21.5 +
    21.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
    21.7 +
    21.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
    21.9 +// of this software and associated documentation files (the "Software"), to deal
   21.10 +// in the Software without restriction, including without limitation the rights
   21.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   21.12 +// copies of the Software, and to permit persons to whom the Software is
   21.13 +// furnished to do so, subject to the following conditions:
   21.14 +
   21.15 +// The above copyright notice and this permission notice shall be included in
   21.16 +// all copies or substantial portions of the Software.
   21.17 +
   21.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   21.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   21.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   21.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   21.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   21.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   21.24 +// THE SOFTWARE.
   21.25 +
   21.26 +import Connectable::*;
   21.27 +import GetPut::*;
   21.28 +import ClientServer::*;
   21.29 +import Processor::*;
   21.30 +import MemArb::*;
   21.31 +import MemTypes::*;
   21.32 +
   21.33 +//AWB includes
   21.34 +`include "asim/provides/low_level_platform_interface.bsh"
   21.35 +`include "asim/provides/soft_connections.bsh"
   21.36 +`include "asim/provides/common_services.bsh"
   21.37 +
   21.38 +// Local includes
   21.39 +`include "asim/provides/processor_library.bsh"
   21.40 +`include "asim/provides/mem_arb.bsh"
   21.41 +`include "asim/provides/instruction_cache.bsh"
   21.42 +`include "asim/provides/data_cache.bsh"
   21.43 +`include "asim/provides/processor.bsh"
   21.44 +
   21.45 +interface Core;
   21.46 +
   21.47 +  // Interface from core to main memory
   21.48 +   interface Client#(MainMemReq,MainMemResp) mmem_client;
   21.49 +
   21.50 +   interface CPUToHost tohost;
   21.51 +	 
   21.52 +   interface AudioIn audio;
   21.53 +
   21.54 +endinterface
   21.55 +
   21.56 +interface AudioIn;
   21.57 + //     interface Put#(AudioProcessorUnit) sampleInput;
   21.58 +      interface Get#(AudioProcessorUnit) sampleOutput;
   21.59 +endinterface      
   21.60 +
   21.61 +module   [CONNECTED_MODULE]  mkCore( Core );
   21.62 +
   21.63 +  // Instantiate the modules
   21.64 +
   21.65 +  Proc proc <- mkProc();
   21.66 +  ICache#(InstReq,InstResp) icache <- mkInstCache();
   21.67 +  DCache#(DataReq,DataResp) dcache <- mkDataCache();
   21.68 +  MemArb marb <- mkMemArb();
   21.69 +
   21.70 +  // Internal connections
   21.71 +
   21.72 +  mkConnection( proc.statsEn_get,   icache.statsEn_put );
   21.73 +  mkConnection( proc.statsEn_get,   dcache.statsEn_put );
   21.74 +  mkConnection( proc.imem_client,   icache.proc_server );
   21.75 +  mkConnection( proc.dmem_client,   dcache.proc_server );
   21.76 +  mkConnection( icache.mmem_client, marb.cache0_server );
   21.77 +  mkConnection( dcache.mmem_client, marb.cache1_server );
   21.78 +
   21.79 +  // Methods
   21.80 +
   21.81 +   interface mmem_client = marb.mmem_client;
   21.82 +
   21.83 +   interface CPUToHost tohost = proc.tohost;
   21.84 +
   21.85 +   interface AudioIn audio = proc.audioIn;
   21.86 +
   21.87 +endmodule

    22.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv	Tue Apr 27 09:03:28 2010 -0400
    22.3 @@ -0,0 +1,94 @@
    22.4 +// The MIT License
    22.5 +
    22.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
    22.7 +
    22.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
    22.9 +// of this software and associated documentation files (the "Software"), to deal
   22.10 +// in the Software without restriction, including without limitation the rights
   22.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   22.12 +// copies of the Software, and to permit persons to whom the Software is
   22.13 +// furnished to do so, subject to the following conditions:
   22.14 +
   22.15 +// The above copyright notice and this permission notice shall be included in
   22.16 +// all copies or substantial portions of the Software.
   22.17 +
   22.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   22.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   22.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   22.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   22.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   22.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   22.24 +// THE SOFTWARE.
   22.25 +
   22.26 +// Author: Kermin Fleming kfleming@mit.edu
   22.27 +
   22.28 +import Connectable::*;
   22.29 +import GetPut::*;
   22.30 +import ClientServer::*;
   22.31 +import FIFO::*;
   22.32 +
   22.33 +//AWB includes
   22.34 +`include "asim/provides/low_level_platform_interface.bsh"
   22.35 +`include "asim/provides/soft_connections.bsh"
   22.36 +`include "asim/provides/common_services.bsh"
   22.37 +
   22.38 +//Local includes
   22.39 +`include "asim/provides/audio_pipe_types.bsh"  //provides Audio Pipeline interface
   22.40 +`include "asim/provides/core.bsh"
   22.41 +
   22.42 +`include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
   22.43 +`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
   22.44 +
   22.45 +module [CONNECTED_MODULE] mkConnectedApplication ();
   22.46 +   Core core <- mkCore;
   22.47 +   Reg#(int) cycle <- mkReg(0);
   22.48 +
   22.49 +  //External memory 
   22.50 +  // I'm not comfortable assuming that the memory subsystem is in order  
   22.51 +  // So I'll insert a completion buffer here.  
   22.52 +  ClientStub_AUDICORERRR client_stub <- mkClientStub_AUDIOCORERRR();   
   22.53 +  // Make this big enough so that several outstanding requests may be supported
   22.54 +  FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
   22.55 +
   22.56 +  // this is for the tracing
   22.57 +  rule printCycles;
   22.58 +    cycle <= cycle+1;
   22.59 +    $fdisplay(stderr, " => Cycle = %d", cycle);
   22.60 +  endrule
   22.61 +
   22.62 +  rule sendMemReq;
   22.63 +    let coreReq <- core.mmem_client.request.get;
   22.64 +    case (coreReq) matches 
   22.65 +      tagged LoadReq .load: begin
   22.66 +                              //Allocate ROB space
   22.67 +                              client_stub.makeRequest_MemoryRequestLoad(load.addr);
   22.68 +                              tags.enq(load.tag);
   22.69 +                            end
   22.70 +      tagged StoreReq .store: begin
   22.71 +                                client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
   22.72 +                              end
   22.73 +    endcase
   22.74 +  endrule
   22.75 +  
   22.76 +  rule receiveMemResp;
   22.77 +    let memResp <- client_stub.getResponse_MemoryRequestLoad();
   22.78 +    tags.deq;
   22.79 +    core.mmem_client.response.put(tagged LoadResp {data:memResp,
   22.80 +                                                   tag: tags.first});
   22.81 +  endrule
   22.82 +
   22.83 +  // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together.
   22.84 +
   22.85 +   rule feedOutput;
   22.86 +     let pipelineData <- core.sampleOutput.get();
   22.87 +     AudioProcessorControl endOfFileTag = EndOfFile;
   22.88 +     AudioProcessorControl sampleTag = Data;
   22.89 +
   22.90 +     case (pipelineData) matches
   22.91 +       tagged EndOfFile: client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
   22.92 +       tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)),
   22.93 +                                                                         zeroExtend(pack(sample)));
   22.94 +     endcase
   22.95 +   endrule
   22.96 +
   22.97 +endmodule

    23.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    23.2 +++ b/modules/bluespec/Pygar/core/audioCorePipeline.bsv~	Tue Apr 27 09:03:28 2010 -0400
    23.3 @@ -0,0 +1,94 @@
    23.4 +// The MIT License
    23.5 +
    23.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
    23.7 +
    23.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
    23.9 +// of this software and associated documentation files (the "Software"), to deal
   23.10 +// in the Software without restriction, including without limitation the rights
   23.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   23.12 +// copies of the Software, and to permit persons to whom the Software is
   23.13 +// furnished to do so, subject to the following conditions:
   23.14 +
   23.15 +// The above copyright notice and this permission notice shall be included in
   23.16 +// all copies or substantial portions of the Software.
   23.17 +
   23.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   23.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   23.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   23.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   23.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   23.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   23.24 +// THE SOFTWARE.
   23.25 +
   23.26 +// Author: Kermin Fleming kfleming@mit.edu
   23.27 +
   23.28 +import Connectable::*;
   23.29 +import GetPut::*;
   23.30 +import ClientServer::*;
   23.31 +import FIFO::*;
   23.32 +
   23.33 +//AWB includes
   23.34 +`include "asim/provides/low_level_platform_interface.bsh"
   23.35 +`include "asim/provides/soft_connections.bsh"
   23.36 +`include "asim/provides/common_services.bsh"
   23.37 +
   23.38 +//Local includes
   23.39 +`include "asim/provides/audio_processor_types.bsh"  //provides Audio Pipeline interface
   23.40 +`include "asim/provides/core.bsh"
   23.41 +
   23.42 +`include "asim/rrr/remote_client_stub_AUDIOCORERRR.bsh"
   23.43 +`include "asim/rrr/remote_server_stub_AUDIOCORERRR.bsh"
   23.44 +
   23.45 +module [CONNECTED_MODULE] mkConnectedApplication ();
   23.46 +   Core core <- mkCore;
   23.47 +   Reg#(int) cycle <- mkReg(0);
   23.48 +
   23.49 +  //External memory 
   23.50 +  // I'm not comfortable assuming that the memory subsystem is in order  
   23.51 +  // So I'll insert a completion buffer here.  
   23.52 +  ClientStub_PROCESSORSYSTEMRRR client_stub <- mkClientStub_PROCESSORSYSTEMRRR();   
   23.53 +  // Make this big enough so that several outstanding requests may be supported
   23.54 +  FIFO#(Bit#(MainMemTagSz)) tags <- mkSizedFIFO(8);
   23.55 +
   23.56 +  // this is for the tracing
   23.57 +  rule printCycles;
   23.58 +    cycle <= cycle+1;
   23.59 +    $fdisplay(stderr, " => Cycle = %d", cycle);
   23.60 +  endrule
   23.61 +
   23.62 +  rule sendMemReq;
   23.63 +    let coreReq <- core.mmem_client.request.get;
   23.64 +    case (coreReq) matches 
   23.65 +      tagged LoadReq .load: begin
   23.66 +                              //Allocate ROB space
   23.67 +                              client_stub.makeRequest_MemoryRequestLoad(load.addr);
   23.68 +                              tags.enq(load.tag);
   23.69 +                            end
   23.70 +      tagged StoreReq .store: begin
   23.71 +                                client_stub.makeRequest_MemoryRequestStore(store.addr,store.data);
   23.72 +                              end
   23.73 +    endcase
   23.74 +  endrule
   23.75 +  
   23.76 +  rule receiveMemResp;
   23.77 +    let memResp <- client_stub.getResponse_MemoryRequestLoad();
   23.78 +    tags.deq;
   23.79 +    core.mmem_client.response.put(tagged LoadResp {data:memResp,
   23.80 +                                                   tag: tags.first});
   23.81 +  endrule
   23.82 +
   23.83 +  // this isn't particularly correct as it doesn't actually connect the processor interfaces, but this should allow me to verify the data path before fully blending the two items together.
   23.84 +
   23.85 +   rule feedOutput;
   23.86 +     let pipelineData <- core.sampleOutput.get();
   23.87 +     AudioProcessorControl endOfFileTag = EndOfFile;
   23.88 +     AudioProcessorControl sampleTag = Data;
   23.89 +
   23.90 +     case (pipelineData) matches
   23.91 +       tagged EndOfFile: client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(endOfFileTag)),?);
   23.92 +       tagged Sample .sample:client_stub.makeRequest_SendProcessedStream(zeroExtend(pack(sampleTag)),
   23.93 +                                                                         zeroExtend(pack(sample)));
   23.94 +     endcase
   23.95 +   endrule
   23.96 +
   23.97 +endmodule

    24.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    24.2 +++ b/modules/bluespec/Pygar/core/audio_core.awb~	Tue Apr 27 09:03:28 2010 -0400
    24.3 @@ -0,0 +1,16 @@
    24.4 +i%name Simple Audio Processor Core 
    24.5 +%desc Instantiates a processor, some caches, and a memory arbiter
    24.6 +
    24.7 +%provides core
    24.8 +
    24.9 +%requires mem_arb
   24.10 +%requires instruction_cache
   24.11 +%requires data_cache
   24.12 +%requires processor
   24.13 +%requires processor_library
   24.14 +
   24.15 +%attributes 6_375
   24.16 +
   24.17 +%public audioCore.bsv
   24.18 +
   24.19 +

    25.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    25.2 +++ b/modules/bluespec/Pygar/core/audio_core_pipe.awb	Tue Apr 27 09:03:28 2010 -0400
    25.3 @@ -0,0 +1,26 @@
    25.4 +%name audio pipeline with soft core
    25.5 +%desc Instantiates a soft core used for audio, wrapped in the audio pipeline interface
    25.6 +
    25.7 +%provides connected_application
    25.8 +
    25.9 +%requires audio_pipe_types
   25.10 +%requires core
   25.11 +%requires funcp_simulated_memory
   25.12 +%requires funcp_base_types
   25.13 +%requires hasim_common
   25.14 +
   25.15 +
   25.16 +%attributes 6_375
   25.17 +
   25.18 +%sources -t BSV	 -v PUBLIC audioCorePipeline.bsv
   25.19 +%sources -t CPP  -v PRIVATE AudioCoreSystem.cpp
   25.20 +%sources -t H    -v PUBLIC AudioCoreSystem.h
   25.21 +%sources -t CPP  -v PRIVATE AudioCoreRRR.cpp
   25.22 +%sources -t H    -v PUBLIC AudioCoreRRR.h
   25.23 +%sources -t RRR  -v PUBLIC AudioCoreRRR.rrr
   25.24 +%sources -t CPP  -v PRIVATE SndfileWavUtil.cpp
   25.25 +%sources -t H	 -v PUBLIC SndfileWavUtil.h
   25.26 +%library /usr/lib/libsndfile.so
   25.27 +
   25.28 +%param SYNTH_BOUNDARY mkConnectedApplication "name of synthesis boundary"
   25.29 +

    26.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    26.2 +++ b/modules/bluespec/Pygar/core/audio_core_pipe.awb~	Tue Apr 27 09:03:28 2010 -0400
    26.3 @@ -0,0 +1,15 @@
    26.4 +%name audio core
    26.5 +%desc Instantiates a soft core used for audio, wrapped in the audio pipeline interface
    26.6 +
    26.7 +%provides audio_pipeline
    26.8 +
    26.9 +%requires core
   26.10 +%requires funcp_simulated_memory
   26.11 +%requires funcp_base_types
   26.12 +%requires hasim_common
   26.13 +
   26.14 +
   26.15 +%attributes 6_375
   26.16 +
   26.17 +%public audioCorePipeline.bsv
   26.18 +

    27.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    27.2 +++ b/modules/bluespec/Pygar/core/audio_core_systems.awb	Tue Apr 27 09:03:28 2010 -0400
    27.3 @@ -0,0 +1,22 @@
    27.4 +%name Single Processor Application
    27.5 +%desc Top level processor. This module wraps a processor, which at its highest level is just a memory stream. 
    27.6 +
    27.7 +%provides connected_application
    27.8 +
    27.9 +%requires audio_pipline
   27.10 +
   27.11 +%attributes 6_375
   27.12 +
   27.13 +%sources -t BSV  -v PUBLIC AudioCorePipeline.bsv
   27.14 +%sources -t CPP  -v PUBLIC AudioCoreSystem.cpp
   27.15 +%sources -t H    -v PUBLIC AudioCoreSystem.h
   27.16 +%sources -t CPP  -v PUBLIC AudioCoreRRR.cpp
   27.17 +%sources -t H    -v PUBLIC AudioCoreRRR.h
   27.18 +%sources -t RRR  -v PUBLIC AudioCoreRRR.rrr
   27.19 +%sources -t CPP  -v PRIVATE SndfileWavUtil.cpp
   27.20 +%sources -t H    -v PUBLIC  SndfileWavUtil.h
   27.21 +
   27.22 +%library /usr/lib/libsndfile.so
   27.23 +
   27.24 +%param SYNTH_BOUNDARY mkConnectedApplication "name of synthesis boundary"
   27.25 +

    28.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    28.2 +++ b/modules/bluespec/Pygar/core/audio_core_systems.awb~	Tue Apr 27 09:03:28 2010 -0400
    28.3 @@ -0,0 +1,21 @@
    28.4 +%name Single Processor Application
    28.5 +%desc Top level processor. This module wraps a processor, which at its highest level is just a memory stream. 
    28.6 +
    28.7 +%provides connected_application
    28.8 +
    28.9 +%requires core
   28.10 +%requires funcp_simulated_memory
   28.11 +%requires funcp_base_types
   28.12 +%requires hasim_common
   28.13 +
   28.14 +%attributes 6_375
   28.15 +
   28.16 +%sources -t BSV  -v PUBLIC ProcessorSystem.bsv
   28.17 +%sources -t CPP  -v PUBLIC ProcessorSystem.cpp
   28.18 +%sources -t H    -v PUBLIC ProcessorSystem.h
   28.19 +%sources -t CPP  -v PUBLIC ProcessorSystemRRR.cpp
   28.20 +%sources -t H    -v PUBLIC ProcessorSystemRRR.h
   28.21 +%sources -t RRR  -v PUBLIC ProcessorSystemRRR.rrr
   28.22 +
   28.23 +%param SYNTH_BOUNDARY mkConnectedApplication "name of synthesis boundary"
   28.24 +

    29.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    29.2 +++ b/modules/bluespec/Pygar/core/audio_pipe_types.awb	Tue Apr 27 09:03:28 2010 -0400
    29.3 @@ -0,0 +1,10 @@
    29.4 +i%name Simple Audio Processor Core 
    29.5 +%desc Instantiates a processor, some caches, and a memory arbiter
    29.6 +
    29.7 +%provides audio_pipe_types
    29.8 +
    29.9 +%attributes 6_375
   29.10 +
   29.11 +%public AudioPipeTypes.bsv
   29.12 +
   29.13 +

    30.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    30.2 +++ b/modules/bluespec/Pygar/core/audio_pipe_types.awb~	Tue Apr 27 09:03:28 2010 -0400
    30.3 @@ -0,0 +1,16 @@
    30.4 +i%name Simple Audio Processor Core 
    30.5 +%desc Instantiates a processor, some caches, and a memory arbiter
    30.6 +
    30.7 +%provides audio_pipe_types
    30.8 +
    30.9 +%requires mem_arb
   30.10 +%requires instruction_cache
   30.11 +%requires data_cache
   30.12 +%requires processor
   30.13 +%requires processor_library
   30.14 +
   30.15 +%attributes 6_375
   30.16 +
   30.17 +%public audioCore.bsv
   30.18 +
   30.19 +

    31.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    31.2 +++ b/modules/bluespec/Pygar/core/olaCore.bsv	Tue Apr 27 09:03:28 2010 -0400
    31.3 @@ -0,0 +1,90 @@
    31.4 +// The MIT License
    31.5 +
    31.6 +// Copyright (c) 2009 Massachusetts Institute of Technology
    31.7 +
    31.8 +// Permission is hereby granted, free of charge, to any person obtaining a copy
    31.9 +// of this software and associated documentation files (the "Software"), to deal
   31.10 +// in the Software without restriction, including without limitation the rights
   31.11 +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   31.12 +// copies of the Software, and to permit persons to whom the Software is
   31.13 +// furnished to do so, subject to the following conditions:
   31.14 +
   31.15 +// The above copyright notice and this permission notice shall be included in
   31.16 +// all copies or substantial portions of the Software.
   31.17 +
   31.18 +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   31.19 +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   31.20 +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   31.21 +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   31.22 +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   31.23 +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   31.24 +// THE SOFTWARE.
   31.25 +
   31.26 +import Connectable::*;
   31.27 +import GetPut::*;
   31.28 +import ClientServer::*;
   31.29 +
   31.30 +import DataCacheBlocking::*;
   31.31 +import InstCacheBlocking::*;
   31.32 +import Processor::*;
   31.33 +import MemArb::*;
   31.34 +import MemTypes::*;
   31.35 +
   31.36 +`include "asim/provides/data_cache.bsh"
   31.37 +`include "asim/provides/instruction_cache.bsh"
   31.38 +`include "asim/provides/processor_library.bsh"
   31.39 +
   31.40 +//interface CoreStats;
   31.41 +//  interface DCacheStats dcache;
   31.42 +  //interface ICacheStats icache;
   31.43 +  //interface ProcStats proc;
   31.44 +//endinterface
   31.45 +
   31.46 +interface Core;
   31.47 +
   31.48 +  // Interface from core to main memory
   31.49 +  interface Client#(MainMemReq,MainMemResp) mmem_client;
   31.50 +
   31.51 +  // Statistics
   31.52 +//  interface CoreStats stats;
   31.53 +
   31.54 +  // CPU to Host
   31.55 +  interface CPUToHost tohost;
   31.56 +
   31.57 +  // Interface to Audio Pipeline
   31.58 +  interface Audio audio;
   31.59 +
   31.60 +endinterface
   31.61 +
   31.62 +(* synthesize *)
   31.63 +module mkCore(Core);
   31.64 +
   31.65 +  // Instantiate the modules
   31.66 +  Proc proc <- mkProc();
   31.67 +  ICache#(InstReq,InstResp) icache <- mkInstCache();
   31.68 +  DCache#(DataReq,DataResp) dcache <- mkDataCache();
   31.69 +  MemArb marb <- mkMemArb();
   31.70 +
   31.71 +  // Internal connections
   31.72 +  mkConnection( proc.statsEn_get,   icache.statsEn_put );
   31.73 +  mkConnection( proc.statsEn_get,   dcache.statsEn_put );
   31.74 +  mkConnection( proc.imem_client,   icache.proc_server );
   31.75 +  mkConnection( proc.dmem_client,   dcache.proc_server );
   31.76 +  mkConnection( icache.mmem_client, marb.cache0_server );
   31.77 +  mkConnection( dcache.mmem_client, marb.cache1_server );
   31.78 +
   31.79 +  // Methods
   31.80 +  interface mmem_client = marb.mmem_client;
   31.81 +
   31.82 +//  interface CoreStats stats;
   31.83 +//    interface dcache = dcache.stats;
   31.84 +//    interface icache = icache.stats;
   31.85 +//    interface proc = proc.stats;
   31.86 +//  endinterface
   31.87 +
   31.88 +  interface CPUToHost tohost = proc.tohost;
   31.89 +
   31.90 +  interface Audio audio = proc.audio;
   31.91 +	
   31.92 +endmodule
   31.93 +

    32.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    32.2 +++ b/modules/bluespec/Pygar/core/processor.awb~	Tue Apr 27 09:03:28 2010 -0400
    32.3 @@ -0,0 +1,13 @@
    32.4 +%name 3-Stage Processor  
    32.5 +%desc 3-Stage Processor, one stage per cycle.
    32.6 +
    32.7 +%provides processor
    32.8 +
    32.9 +%attributes 6_375
   32.10 +
   32.11 +%public Processor.bsv ProcTypes.bsv
   32.12 +%public Processor.dic
   32.13 +
   32.14 +
   32.15 +
   32.16 +

    33.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    33.2 +++ b/modules/bluespec/Pygar/core/processor_library.a	Tue Apr 27 09:03:28 2010 -0400
    33.3 @@ -0,0 +1,9 @@
    33.4 +%name Processor Audio Library 
    33.5 +%desc Some generally useful modules, found in the processor cores
    33.6 +
    33.7 +%provides processor_library
    33.8 +
    33.9 +%attributes 6_375
   33.10 +
   33.11 +%public Trace.bsv BFIFO.bsv MemTypes.bsv BRegFile.bsv BranchPred.bsv
   33.12 +