# HG changeset patch # User punk # Date 1272633218 14400 # Node ID 9830ff8fb0bd9e4dccc4e3fe9bae2239efe1204b # Parent 3958de09a7c1eae236351f2507591977b69f7a83 [svn r30] Forgot a file diff -r 3958de09a7c1 -r 9830ff8fb0bd modules/bluespec/Pygar/lab4/ProcTrace.bsv --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/lab4/ProcTrace.bsv Fri Apr 30 09:13:38 2010 -0400 @@ -0,0 +1,109 @@ + +import Trace::*; + +//---------------------------------------------------------------------- +// Trace +//---------------------------------------------------------------------- + +instance Traceable#(Instr); + + function Action traceTiny( String loc, String ttag, Instr inst ); + case ( inst ) matches + + tagged LW .it : $fdisplay(stderr, " => %s:%s lw", loc, ttag ); + tagged SW .it : $fdisplay(stderr, " => %s:%s sw", loc, ttag ); + + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addi", loc, ttag ); + tagged SLTI .it : $fdisplay(stderr, " => %s:%s sli", loc, ttag ); + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sliu", loc, ttag ); + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi", loc, ttag ); + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori", loc, ttag ); + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori", loc, ttag ); + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui", loc, ttag ); + + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll", loc, ttag ); + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl", loc, ttag ); + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra", loc, ttag ); + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv", loc, ttag ); + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv", loc, ttag ); + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav", loc, ttag ); + + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu", loc, ttag ); + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu", loc, ttag ); + tagged AND .it : $fdisplay(stderr, " => %s:%s and", loc, ttag ); + tagged OR .it : $fdisplay(stderr, " => %s:%s or", loc, ttag ); + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor", loc, ttag ); + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor", loc, ttag ); + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt", loc, ttag ); + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu", loc, ttag ); + + tagged J .it : $fdisplay(stderr, " => %s:%s j", loc, ttag ); + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal", loc, ttag ); + tagged JR .it : $fdisplay(stderr, " => %s:%s jr", loc, ttag ); + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr", loc, ttag ); + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq", loc, ttag ); + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne", loc, ttag ); + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez", loc, ttag ); + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz", loc, ttag ); + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz", loc, ttag ); + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez", loc, ttag ); + + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0", loc, ttag ); + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0", loc, ttag ); + + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s ill", loc, ttag ); + + endcase + endfunction + + function Action traceFull( String loc, String ttag, Instr inst ); + case ( inst ) matches + + tagged LW .it : $fdisplay(stderr, " => %s:%s lw r%0d, 0x%x(r%0d)", loc, ttag, it.rdst, it.offset, it.rbase ); + tagged SW .it : $fdisplay(stderr, " => %s:%s sw r%0d, 0x%x(r%0d)", loc, ttag, it.rsrc, it.offset, it.rbase ); + + tagged ADDIU .it : $fdisplay(stderr, " => %s:%s addiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged SLTI .it : $fdisplay(stderr, " => %s:%s slti r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged SLTIU .it : $fdisplay(stderr, " => %s:%s sltiu r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged ANDI .it : $fdisplay(stderr, " => %s:%s andi r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged ORI .it : $fdisplay(stderr, " => %s:%s ori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged XORI .it : $fdisplay(stderr, " => %s:%s xori r%0d, r%0d, 0x%x", loc, ttag, it.rdst, it.rsrc, it.imm ); + tagged LUI .it : $fdisplay(stderr, " => %s:%s lui r%0d, 0x%x", loc, ttag, it.rdst, it.imm ); + + tagged SLL .it : $fdisplay(stderr, " => %s:%s sll r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); + tagged SRL .it : $fdisplay(stderr, " => %s:%s srl r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); + tagged SRA .it : $fdisplay(stderr, " => %s:%s sra r%0d, r%0d, %0d", loc, ttag, it.rdst, it.rsrc, it.shamt ); + tagged SLLV .it : $fdisplay(stderr, " => %s:%s sllv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); + tagged SRLV .it : $fdisplay(stderr, " => %s:%s srlv r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); + tagged SRAV .it : $fdisplay(stderr, " => %s:%s srav r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc, it.rshamt ); + + tagged ADDU .it : $fdisplay(stderr, " => %s:%s addu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged SUBU .it : $fdisplay(stderr, " => %s:%s subu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged AND .it : $fdisplay(stderr, " => %s:%s and r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged OR .it : $fdisplay(stderr, " => %s:%s or r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged XOR .it : $fdisplay(stderr, " => %s:%s xor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged NOR .it : $fdisplay(stderr, " => %s:%s nor r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged SLT .it : $fdisplay(stderr, " => %s:%s slt r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + tagged SLTU .it : $fdisplay(stderr, " => %s:%s sltu r%0d, r%0d, r%0d", loc, ttag, it.rdst, it.rsrc1, it.rsrc2 ); + + tagged J .it : $fdisplay(stderr, " => %s:%s j 0x%x", loc, ttag, it.target ); + tagged JAL .it : $fdisplay(stderr, " => %s:%s jal 0x%x", loc, ttag, it.target ); + tagged JR .it : $fdisplay(stderr, " => %s:%s jr r%0d", loc, ttag, it.rsrc ); + tagged JALR .it : $fdisplay(stderr, " => %s:%s jalr r%0d", loc, ttag, it.rsrc ); + tagged BEQ .it : $fdisplay(stderr, " => %s:%s beq r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); + tagged BNE .it : $fdisplay(stderr, " => %s:%s bne r%0d, r%0d, 0x%x", loc, ttag, it.rsrc1, it.rsrc2, it.offset ); + tagged BLEZ .it : $fdisplay(stderr, " => %s:%s blez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + tagged BGTZ .it : $fdisplay(stderr, " => %s:%s bgtz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + tagged BLTZ .it : $fdisplay(stderr, " => %s:%s bltz r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + tagged BGEZ .it : $fdisplay(stderr, " => %s:%s bgez r%0d, 0x%x", loc, ttag, it.rsrc, it.offset ); + + tagged MFC0 .it : $fdisplay(stderr, " => %s:%s mfc0 r%0d, cpr%0d", loc, ttag, it.rdst, it.cop0src ); + tagged MTC0 .it : $fdisplay(stderr, " => %s:%s mtc0 r%0d, cpr%0d", loc, ttag, it.rsrc, it.cop0dst ); + + tagged ILLEGAL : $fdisplay(stderr, " => %s:%s illegal instruction", loc, ttag ); + + endcase + endfunction + +endinstance + diff -r 3958de09a7c1 -r 9830ff8fb0bd modules/bluespec/Pygar/lab4/audio_processor_library.awb --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/lab4/audio_processor_library.awb Fri Apr 30 09:13:38 2010 -0400 @@ -0,0 +1,10 @@ +%name External Trace Processor Library +%desc Some generally useful modules, found in the processor cores, no trace. + +%provides processor_library + +%requires trace + +%attributes PYGAR + +%public BFIFO.bsv MemTypes.bsv FIFOUtility.bsv GetPutExt.bsv SFIFO.bsv CBUFF.bsv BRegFile.bsv BranchPred.bsv diff -r 3958de09a7c1 -r 9830ff8fb0bd modules/bluespec/Pygar/lab4/audio_processor_library.awb~ --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/modules/bluespec/Pygar/lab4/audio_processor_library.awb~ Fri Apr 30 09:13:38 2010 -0400 @@ -0,0 +1,8 @@ +%name No-Trace Processor Library +%desc Some generally useful modules, found in the processor cores, no trace. + +%provides processor_library + +%attributes PYGAR + +%public BFIFO.bsv MemTypes.bsv FIFOUtility.bsv GetPutExt.bsv SFIFO.bsv CBUFF.bsv BRegFile.bsv BranchPred.bsv