# HG changeset patch # User punk # Date 1273539649 14400 # Node ID 90fa9b289aab976dc08859e7b96ceaa5c6b004e5 # Parent 74d2fe78f36a7b8d980643cfc699951a37dac0e2 [svn r63] synthesis boundaries diff -r 74d2fe78f36a -r 90fa9b289aab modules/bluespec/Pygar/lab4/BRegFile.bsv --- a/modules/bluespec/Pygar/lab4/BRegFile.bsv Mon May 10 20:31:25 2010 -0400 +++ b/modules/bluespec/Pygar/lab4/BRegFile.bsv Mon May 10 21:00:49 2010 -0400 @@ -11,15 +11,15 @@ // Register file module //----------------------------------------------------------- -interface BRegFile #(type index_t, type data_t); - method Action upd(index_t addr, data_t data); - method data_t sub(index_t addr); +interface BRFile; + method Action wr( Rindx rindx, Bit#(32) data ); + method Action Value Bit#(32) rd1( Rindx rindx ); + method Action Value Bit#(32) rd2( Rindx rindx ); endinterface - (* doc = "synthesis attribute ram_style mkBRegFile distributed;" *) (* synthesize *) -module mkBRegFile(RegFile#(index_t, data_t)) +module mkBRegFile(BRFile) provisos (Bits#(index_t, size_index), Bits#(data_t, size_data), Eq#(index_t), @@ -28,17 +28,31 @@ LUTRAM#(index_t, data_t) rf <- mkLUTRAMU_RegFile(); RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire(); - method Action upd (index_t r, data_t d); - rf.upd(r,d); - rw.wset(tuple2(r,d)); + method Action wr( Rindx rindx, Bit#(32) data ); + rf.upd( rindx, data ); + rw.wset(tuple2(rindex,data)); endmethod - method data_t sub (index_t r); - case (rw.wget()) matches - tagged Valid {.wr, .d} : - return (wr == r) ? d : rf.sub(r); - tagged Invalid : return rf.sub(r); - endcase + method Bit#(32) rd1 (Rindx r); + if (r == 0) return 0; + else begin + case (rw.wget()) matches + tagged Valid {.wr, .d} : + return (wr == r) ? d : rf.sub(r); + tagged Invalid : return rf.sub(r); + endcase + end + endmethod + + method Bit#(32) rd2 (Rindx r); + if (r == 0) return 0; + else begin + case (rw.wget()) matches + tagged Valid {.wr, .d} : + return (wr == r) ? d : rf.sub(r); + tagged Invalid : return rf.sub(r); + endcase + end endmethod endmodule