# HG changeset patch
# User punk
# Date 1273513632 14400
# Node ID 52f9a257c2ba8dcec38e2f2b2418b86525940a1b
# Parent  b5be746a0d743ea95edfce0aec89859e4a689300
[svn r59] LUTRAMing

diff -r b5be746a0d74 -r 52f9a257c2ba modules/bluespec/Pygar/lab4/BRegFile.bsv
--- a/modules/bluespec/Pygar/lab4/BRegFile.bsv	Mon May 10 12:17:52 2010 -0400
+++ b/modules/bluespec/Pygar/lab4/BRegFile.bsv	Mon May 10 13:47:12 2010 -0400
@@ -2,6 +2,11 @@
 import RWire::*;
 import ProcTypes::*;
 
+`include "asim/provides/low_level_platform_interface.bsh"
+`include "asim/provides/soft_connections.bsh"
+`include "asim/provides/fpga_components.bsh"
+`include "asim/provides/common_services.bsh"
+
 //-----------------------------------------------------------
 // Register file module
 //-----------------------------------------------------------
@@ -17,7 +22,7 @@
 	     Eq#(index_t),
 	     Bounded#(index_t) );
 
-   RegFile#(index_t, data_t) rf <- mkRegFileWCF(minBound, maxBound);
+   LUTRAM#(index_t, data_t) rf <- mkLUTRAM_RegFile();
    RWire#(Tuple2#(index_t, data_t)) rw <-mkRWire();
 
    method Action upd (index_t r, data_t d);